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path: root/mppa_k1c/PostpassSchedulingOracle.ml
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* Adding indirect calls (icall instruction)Cyril SIX2019-01-291-3/+5
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* Added sxwd and zxwd supportCyril SIX2019-01-221-5/+8
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* -O0 will not perform postpass schedulingCyril SIX2019-01-181-1/+1
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* Minor bug in encode_immCyril SIX2019-01-181-2/+2
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* Minor bug fixesCyril SIX2019-01-171-2/+2
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* Corrected a bug in Pallocframe expansion with va_argsCyril SIX2019-01-171-0/+1
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* Merge correctionsCyril SIX2019-01-171-5/+6
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* Corrected a bug in PostlassSchedulingOracle:intlist provoking cyclesCyril SIX2019-01-171-1/+1
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* Added the rest of the instructions info (manually)Cyril SIX2019-01-161-47/+160
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* More instruction definitions in the oracleCyril SIX2019-01-161-11/+34
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* Debugged latency generation. We are able to produce bundlesCyril SIX2019-01-151-23/+78
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* Pfreeframe and Pallocframe raise "OpaqueInstruction". Splitting bb to ↵Cyril SIX2019-01-151-18/+55
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* Added RA as possible location + control flow infoCyril SIX2019-01-111-6/+12
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* Adding Mem as a possible location for accessesCyril SIX2019-01-111-23/+31
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* Replaced the faulty bundlize_solution functionCyril SIX2019-01-111-28/+43
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* [BROKEN] trying to link the test in mppa_k1c/unittest/postpass_testCyril SIX2019-01-111-33/+18
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* [BROKEN] Added infos about sd, infinite loop somewhereCyril SIX2019-01-091-5/+23
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* Adding more Asmblock instructions to PostpassSchedulingOracleCyril SIX2019-01-081-14/+108
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* Raccordement de InstructionScheduler.ml à PostpassSchedulingOracle.mlCyril SIX2019-01-081-4/+94
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* Latency constraints building done in PostpassSchedulingOracle.mlCyril SIX2019-01-081-16/+28
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* Reorganized PostpassOracle to separate asmblock instructions from real ↵Cyril SIX2019-01-081-72/+111
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* Finished the immediate recognition part, started latency constraintsCyril SIX2019-01-071-19/+78
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* [BROKEN] Début d'oracleCyril SIX2018-12-201-1/+105
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* Added a simple postpass oracle that splits a bblock into single instruction ↵Cyril SIX2018-12-171-0/+18
bundles
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