aboutsummaryrefslogtreecommitdiffstats
path: root/mppa_k1c
Commit message (Expand)AuthorAgeFilesLines
* Minor bug in encode_immCyril SIX2019-01-181-2/+2
* Minor bug fixesCyril SIX2019-01-171-2/+2
* Ommited a ;; in va_arg_start macroCyril SIX2019-01-171-0/+1
* Corrected a bug in Pallocframe expansion with va_argsCyril SIX2019-01-172-3/+7
* Merge correctionsCyril SIX2019-01-172-74/+75
* Merge branch 'mppa_k1c' into mppa_postpassCyril SIX2019-01-174-79/+80
|\
| * Added an error message for 32-bits division and moduloCyril SIX2018-12-111-13/+13
| * Fixed div64 and mod64Cyril SIX2018-12-111-0/+1
| * Fixed that fnegd and negd had been invertedCyril SIX2018-12-071-1/+1
| * Fixed bundles (back to 1 instruction per bundle)Cyril SIX2018-12-071-65/+65
* | Corrected a bug in PostlassSchedulingOracle:intlist provoking cyclesCyril SIX2019-01-171-1/+1
* | Added the rest of the instructions info (manually)Cyril SIX2019-01-161-47/+160
* | More instruction definitions in the oracleCyril SIX2019-01-162-12/+36
* | Debugged latency generation. We are able to produce bundlesCyril SIX2019-01-151-23/+78
* | Pfreeframe and Pallocframe raise "OpaqueInstruction". Splitting bb to isolate...Cyril SIX2019-01-151-18/+55
* | Added RA as possible location + control flow infoCyril SIX2019-01-111-6/+12
* | Adding Mem as a possible location for accessesCyril SIX2019-01-111-23/+31
* | Merge branch 'unittest' of gricad-gitlab.univ-grenoble-alpes.fr:sixcy/CompCer...Cyril SIX2019-01-111-2/+3
|\ \
| * | flush stdoutSylvain Boulmé2019-01-111-0/+1
| * | quick and dirty Makefile fixesSylvain Boulmé2019-01-111-2/+3
* | | Replaced the faulty bundlize_solution functionCyril SIX2019-01-111-28/+43
|/ /
* | [BROKEN] trying to link the test in mppa_k1c/unittest/postpass_testCyril SIX2019-01-114-35/+43
* | [BROKEN] Added infos about sd, infinite loop somewhereCyril SIX2019-01-091-5/+23
* | Adding more Asmblock instructions to PostpassSchedulingOracleCyril SIX2019-01-081-14/+108
* | Raccordement de InstructionScheduler.ml à PostpassSchedulingOracle.mlCyril SIX2019-01-081-4/+94
* | Latency constraints building done in PostpassSchedulingOracle.mlCyril SIX2019-01-081-16/+28
* | Reorganized PostpassOracle to separate asmblock instructions from real instru...Cyril SIX2019-01-081-72/+111
* | Fixed warnings in InstructionSchedulerCyril SIX2019-01-082-21/+24
* | Finished the immediate recognition part, started latency constraintsCyril SIX2019-01-071-19/+78
* | [BROKEN] Début d'oracleCyril SIX2018-12-203-1/+1068
* | Added a simple postpass oracle that splits a bblock into single instruction b...Cyril SIX2018-12-175-4/+32
* | Generalizing PostpassScheduling to include bblock splittingCyril SIX2018-12-053-41/+98
* | Moving size_blocks from Asmblockgen to AsmblockCyril SIX2018-12-052-9/+8
* | Renaming PostpassSchedulingProof -> PostpassSchedulingproofCyril SIX2018-12-051-0/+0
* | Added definitions and proof sketch for PostpassSchedulingCyril SIX2018-12-042-40/+110
* | Tout début de développement d'un postpass Asmblock en CoqCyril SIX2018-12-032-0/+135
|/
* Introducing ;; as Pcomma in Asm.vCyril SIX2018-12-032-65/+67
* Finished implementation of va_arg + testing doneCyril SIX2018-11-301-4/+8
* Wrote some tests on va_arg, need to implement __compcert_va_int32 & cieCyril SIX2018-11-281-5/+4
* mppa_k1c compilesCyril SIX2018-11-282-9/+3
* compilation Asmexpandaux both for x86/ and mppa_k1c/Sylvain Boulmé2018-11-282-3/+5
* Compiles for x86 and mppa_k1c (except Asmexpandaux.ml)Sylvain Boulmé2018-11-271-0/+8
* Moved some files to mppa_k1c/lib ; reworked configure and Makefile to allow thatCyril SIX2018-11-263-1585/+322
* Changed ABI to match GCC - interoperability not tested yetCyril SIX2018-11-237-167/+170
* Mise à jour vis à vis de CompCert 3.4Cyril SIX2018-11-216-8/+35
* Modified "Asmgen.*" error messages to "Asmblockgen.*"Cyril SIX2018-11-161-12/+12
* Merge branch 'mppa_asmbloc_nobreg' into mppa_k1cCyril SIX2018-11-1415-3541/+9460
|\
| * Déterminisme prouvé -> Tout est prouvéCyril SIX2018-11-081-1/+59
| * Proved non_empty_bblock_refl (was Admitted)Cyril SIX2018-11-081-4/+4
| * Proved MBstore -> all instructions are provedCyril SIX2018-11-082-12/+25
generated by cgit (git 2.34.1) at 2024-07-04 02:07:16 +0000