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* Merge branch 'master' into merge_master_8.13.1Sylvain Boulmé2021-03-231-3/+3
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| * Replace `omega` tactic with `lia`, continuedXavier Leroy2021-01-131-1/+1
| * Replace `omega` tactic with `lia`Xavier Leroy2020-12-291-2/+2
* | Merge github.com:AbsInt/CompCert into kvx-workv3.8_kvx_instructions_fixedDavid Monniaux2020-12-081-9/+15
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| * Remove Pfcfi, Pfcfiu, Pfctiu pseudoinstructionsXavier Leroy2020-12-061-9/+15
* | Merge tag 'v3.6' of https://github.com/AbsInt/CompCert into mppa-work-upstrea...David Monniaux2019-09-201-2/+2
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| * Fix compile for architectures other than AArch64 (#192)Bernhard Schommer2019-08-171-2/+2
* | various fixesDavid Monniaux2019-07-191-1/+0
* | helpers broke compilationDavid Monniaux2019-07-191-2/+1
* | Merge branch 'master' of https://github.com/AbsInt/CompCert into mppa-work-up...David Monniaux2019-07-191-10/+18
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| * Give formal semantics to some built-in functions and run-time functionsXavier Leroy2019-07-171-10/+15
* | Merge branch 'if-conversion' of https://github.com/AbsInt/CompCert into mppa-...David Monniaux2019-06-031-0/+21
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| * Provide a float select operation for PowerPC. (#173)Bernhard Schommer2019-05-281-2/+3
| * PowerPC: add SelectOp.select functionXavier Leroy2019-05-261-0/+20
* | seems like powerpc runs but the result segfaultsDavid Monniaux2019-03-221-2/+26
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* Extend builtin arguments with a pointer addition operator, continuedXavier Leroy2017-07-061-0/+3
* Hybrid 64bit/32bit PowerPC portBernhard Schommer2017-05-031-4/+5
* RISC-V port and assorted changesXavier Leroy2017-04-281-0/+10
* Use "Local" as prefixXavier Leroy2017-02-131-1/+1
* Support for 64-bit architectures: update the PowerPC portXavier Leroy2016-10-011-13/+21
* Added not merged destruction of Archi. Bug 17450Bernhard Schommer2015-10-201-0/+2
* Merge remote-tracking branch 'origin/master' into named-externalsBernhard Schommer2015-10-201-0/+4
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| * bug 17392: remove trailing whitespace in source filesMichael Schmidt2015-10-141-154/+154
| * Use PowerPC 64 bits instructions (when available) for int<->FP conversions.Xavier Leroy2015-09-131-0/+6
* | Updated PR by removing whitespaces. Bug 17450.Bernhard Schommer2015-10-201-152/+152
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* Adapt the PowerPC port to the new builtin representation.Xavier Leroy2015-08-211-3/+3
* Updating the PowerPC and ARM ports.Xavier Leroy2015-03-271-0/+16
* Merge of "newspilling" branch:xleroy2014-07-231-8/+116
* Refactoring: move symbol_offset into Genv.xleroy2014-05-241-15/+8
* Updated the proofs.xleroy2014-04-121-1/+3
* Constprop: use "not" for "xorimm(-1)"; optimize == 1 and != 0 comparisons ove...xleroy2014-04-091-10/+36
* Add option -Os to optimize for code size rather than for execution speed.xleroy2014-02-191-1/+3
* powerpc/: new unary operation "addsymbol"xleroy2013-11-171-13/+36
* Floats.v, Nan.v: hard-wire the general shape of binop_pl, so that no axioms xleroy2013-09-141-5/+0
* Optimize integer divisions by positive constants, turning them intoxleroy2013-07-291-45/+29
* Updated to new CminorSelxleroy2013-04-301-2/+2
* Big merge of the newregalloc-int64 branch. Lots of changes in two directions:xleroy2013-04-201-15/+33
* Ported to Coq 8.4pl1. Merge of branches/coq-8.4.xleroy2013-01-291-12/+12
* Remove some useless "Require".xleroy2012-12-301-2/+0
* Merge of branch seq-and-or. See Changelog for details.xleroy2012-10-061-70/+89
* Remove Val.is_true and Val.is_false, no longer used.xleroy2012-08-061-8/+2
* Micro-optimization of (x & mask) >>s amount into a rolm when mask >= 0.xleroy2012-07-091-10/+18
* Factor out the evaluation of the float constant in intuoffloat.xleroy2012-07-011-12/+13
* CSE: add recognition of some combined operators, conditions, and addressing m...xleroy2012-05-261-8/+4
* Hack with nxorxleroy2012-05-181-0/+3
* PowerPC: remove the fmadd and fmsub operators/Asm instructionsxleroy2012-03-071-13/+2
* Take advantage of Cmaskzero and Cmasknotzero.xleroy2012-02-241-0/+23
* Improved instruction selection for "notint".xleroy2012-02-241-8/+19
* Merge of the "volatile" branch:xleroy2012-02-041-0/+25
* powerpc/SelectOp: optimize the pattern ((x >>s N) & N1) & N2 common in a cert...xleroy2012-01-211-0/+15