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* Merge remote-tracking branch 'origin/kvx-work' into merge_master_8.13.1Cyril SIX2021-06-011-3/+18
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| * Removing addptrofs draft, next will be mergingLéo Gourdin2021-04-091-1/+0
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| * Important commit on expansions' mini CSE, and a draft for addptrofsLéo Gourdin2021-04-061-3/+3
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| * Now a more general way to perform imm operationsLéo Gourdin2021-03-301-2/+1
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| * Refactoring the mayundef OP to be more general...Léo Gourdin2021-03-301-2/+0
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| * Adding more expansions, improving miniCSE, and tuning prepassLéo Gourdin2021-03-261-2/+20
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| * Adding a mini CSE pass in the expansion oracleLéo Gourdin2021-03-061-2/+3
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* | Merge branch 'master' into merge_master_8.13.1Sylvain Boulmé2021-03-231-2/+2
|\ \ | |/ |/| | | | | | | | | | | | | PARTIAL MERGE (PARTLY BROKEN). See unsolved conflicts in: aarch64/TO_MERGE and riscV/TO_MERGE WARNING: interface of va_args and assembly sections have changed
| * Replace `omega` tactic with `lia`Xavier Leroy2020-12-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | Since Coq 8.12, `omega` is flagged as deprecated and scheduled for removal. Also replace CompCert's homemade tactics `omegaContradiction`, `xomega`, and `xomegaContradiction` with `lia` and `extlia`. Turn back on the deprecation warning for uses of `omega`. Make the proof of `Ctypes.sizeof_pos` more robust to variations in `lia`.
* | Merge remote-tracking branch 'origin/riscV-cmov' into riscv-workLéo Gourdin2021-03-021-0/+15
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| * | begin implementing selectDavid Monniaux2021-02-021-0/+11
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| * | bits to floatDavid Monniaux2021-02-011-0/+2
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| * | Obits_of_single etcDavid Monniaux2021-02-011-0/+2
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* | Proof of fsval condition cmp okLéo Gourdin2021-03-011-13/+11
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* | [Admitted checker] Duplicating Asm Ceq/Cne and draft checker proofLéo Gourdin2021-02-111-0/+4
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* | All Ocmp expanded in RTLLéo Gourdin2021-02-031-0/+6
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* | Ccomp for longLéo Gourdin2021-02-031-0/+11
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* | Ccompu expansionLéo Gourdin2021-02-021-0/+2
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* | Expansion of Ccompimm in RTL [Admitted checker]Léo Gourdin2021-02-021-0/+9
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* RISC-V port and assorted changesXavier Leroy2017-04-281-0/+173
This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes. The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/ This port required the following additional changes: - Integers: More properties about shrx - SelectOp: now provides smart constructors for mulhs and mulhu - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu. - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert. Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library. - test/: add SIMU make variable to run tests through a simulator - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers commit da14495c01cf4f66a928c2feff5c53f09bde837f Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Thu Apr 13 17:36:10 2017 +0200 RISC-V port, continued Now working on Asmgen. commit 36f36eb3a5abfbb8805960443d087b6a83e86005 Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Wed Apr 12 17:26:39 2017 +0200 RISC-V port, first steps This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64). Work in progress.
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