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* Removing addptrofs draft, next will be mergingLéo Gourdin2021-04-091-2/+0
* Important commit on expansions' mini CSE, and a draft for addptrofsLéo Gourdin2021-04-061-7/+10
* a more general way to manage special registers before introducing SPLéo Gourdin2021-03-301-51/+47
* Now a more general way to perform imm operationsLéo Gourdin2021-03-301-2/+5
* Refactoring the mayundef OP to be more general...Léo Gourdin2021-03-301-3/+7
* bugfix and printOpLéo Gourdin2021-03-261-0/+6
* Adding more expansions, improving miniCSE, and tuning prepassLéo Gourdin2021-03-261-2/+8
* Merge remote-tracking branch 'origin/riscv-work' into riscv-work-fpinit-stillexpLéo Gourdin2021-03-061-2/+3
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| * Adding a mini CSE pass in the expansion oracleLéo Gourdin2021-03-061-2/+3
* | [Admitted checker] Oracle expansion for float/float32 constant initLéo Gourdin2021-03-021-4/+4
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* Merge remote-tracking branch 'origin/riscV-cmov' into riscv-workLéo Gourdin2021-03-021-0/+5
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| * Adding missing operators in PrintOp for debuggingLéo Gourdin2021-02-251-0/+5
* | Try to save values in virtual registers during expansionLéo Gourdin2021-03-011-5/+17
* | Proof of fsval condition cmp okLéo Gourdin2021-03-011-2/+2
* | cond and branches expandedLéo Gourdin2021-02-061-0/+30
* | Ccomp for longLéo Gourdin2021-02-031-0/+10
* | Ccompu expansionLéo Gourdin2021-02-021-0/+2
* | Expansion of Ccompimm in RTL [Admitted checker]Léo Gourdin2021-02-021-0/+12
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* RISC-V port and assorted changesXavier Leroy2017-04-281-0/+166
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