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* ccomp profilingLéo Gourdin2022-01-051-0/+3
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* Merge branch 'master' of https://github.com/AbsInt/CompCert into towards_3.10David Monniaux2021-09-271-1/+1
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| * Add support to clightgen for generating Csyntax AST as .v filesXavier Leroy2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | As proposed in #404. This is presented as a new option `-clight` to the existing `clightgen` tool. Revise clightgen testing to test the Csyntax output in addition to the Clight output.
* | Merge branch 'master' into merge_master_8.13.1Sylvain Boulmé2021-03-231-2/+3
|\| | | | | | | | | | | | | | | | | PARTIAL MERGE (PARTLY BROKEN). See unsolved conflicts in: aarch64/TO_MERGE and riscV/TO_MERGE WARNING: interface of va_args and assembly sections have changed
| * Testing calling conventions and interoperability with another C compilerXavier Leroy2021-01-181-1/+1
| | | | | | | | Using a combination of fixed and randomly-generated function signatures.
* | k1c -> kvx changesDavid Monniaux2020-05-261-1/+1
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* | fix broken test MakefileDavid Monniaux2020-03-271-1/+3
| | | | | | | | fix math.h so that it does special things only on K1C
* | More work on test, regression/packedstruct1.c and regression/varargs2.c ↵Cyril SIX2019-09-201-1/+5
| | | | | | | | don't pass
* | Desactivating CompCert tests taking too longCyril SIX2019-09-191-1/+3
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* Add tests for clightgenXavier Leroy2018-06-011-0/+8
| | | | Also: add "parallel" entry to test/Makefile for parallel execution of tests.
* test/ : stop at first error in "make all"Xavier Leroy2017-08-261-1/+1
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* test/: add a CCOMPOPTS make variable to pass additional compile-time flagsXavier Leroy2017-08-261-1/+1
| | | | E.g. "-Os" for testing in "optimize for size" mode, or "-mthumb" for testing ARM in Thumb2 mode.
* RISC-V port and assorted changesXavier Leroy2017-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes. The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/ This port required the following additional changes: - Integers: More properties about shrx - SelectOp: now provides smart constructors for mulhs and mulhu - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu. - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert. Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library. - test/: add SIMU make variable to run tests through a simulator - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers commit da14495c01cf4f66a928c2feff5c53f09bde837f Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Thu Apr 13 17:36:10 2017 +0200 RISC-V port, continued Now working on Asmgen. commit 36f36eb3a5abfbb8805960443d087b6a83e86005 Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Wed Apr 12 17:26:39 2017 +0200 RISC-V port, first steps This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64). Work in progress.
* Updates to the local test suiteXavier Leroy2016-07-241-3/+0
| | | | | | | - Adjust parameters to bring the running time of each test closer to 1 second - compression/arcode.c: array access one past - "inline" -> "static inline" - Remove cchecklink support
* test/regression: test packedstruct1 only if unaligned accesses are supported.Xavier Leroy2015-08-211-1/+1
| | | | Also: exit on error when a test fails.
* PowerPC port: refactored the expansion of built-in functions andxleroy2014-07-281-0/+3
| | | | | | | | | | pseudo-instructions so that it does not need to be re-done in cchecklink. cchecklink: updated accordingly. testsuite: compile with -sdump and run cchecklink if supported. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2553 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
* Presimplification SimplVolatile: cleaned up and integrated.xleroy2011-08-181-0/+3
| | | | | | test/*/Makefile: normalized 'bench' target git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@1717 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
* Improved test harnessxleroy2011-03-101-0/+10
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@1598 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
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