diff options
| author | Brad Smith <brad@comstyle.com> | 2022-08-29 03:37:08 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-29 09:37:08 +0200 |
| commit | 50836f2a04575402aa61a256fe7047c16610992f (patch) | |
| tree | d213a8a969c30c01034400c7bd94fe82aaa00eda | |
| parent | c9f8b8e598808775bf4e5072aa47c94625677f7c (diff) | |
| download | compcert-50836f2a04575402aa61a256fe7047c16610992f.tar.gz compcert-50836f2a04575402aa61a256fe7047c16610992f.zip | |
configure: recognize riscv32 and riscv64 for RISC-V targets (#448)
| -rwxr-xr-x | configure | 5 |
1 files changed, 3 insertions, 2 deletions
@@ -65,6 +65,7 @@ Supported targets: For x86 targets, the "x86_32-" prefix can also be written "ia32-" or "i386-". For x86 targets, the "x86_64-" prefix can also be written "amd64-". For AArch64 targets, the "aarch64-" prefix can also be written "arm64-". +For RISC-V targets, the "rv32-" or "rv64-" prefix can also be written "riscv32-" or "riscv64-". For PowerPC targets, the "ppc-" prefix can be refined into: ppc64- PowerPC 64 bits @@ -186,9 +187,9 @@ case "$target" in arch="powerpc"; model="ppc64"; endianness="big"; bitsize=32;; e5500-*) arch="powerpc"; model="e5500"; endianness="big"; bitsize=32;; - rv32-*) + riscv32-*|rv32-*) arch="riscV"; model="32"; endianness="little"; bitsize=32;; - rv64-*) + riscv64-*|rv64-*) arch="riscV"; model="64"; endianness="little"; bitsize=64;; aarch64-*|arm64-*) arch="aarch64"; model="default"; endianness="little"; bitsize=64;; |