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authorXavier Leroy <xavier.leroy@college-de-france.fr>2019-07-12 11:42:25 +0200
committerXavier Leroy <xavierleroy@users.noreply.github.com>2019-07-17 09:16:00 +0200
commit8b0de52ffa302298abe8d0d6e3b6ed339a2354ba (patch)
treefcfdb40451908865ba706e184ff434a847b7711b /riscV
parentdc5dc1da4cfa10647d13f393b6685f962b9b9faa (diff)
downloadcompcert-8b0de52ffa302298abe8d0d6e3b6ed339a2354ba.tar.gz
compcert-8b0de52ffa302298abe8d0d6e3b6ed339a2354ba.zip
Add floating-point square root and fused multiply-add
We just lift the corresponding functions from Flocq and add the computation of NaN payloads. NaN payloads for FMA are described in the ARM and RISC-V specifications, and were determined experimentally for x86 and for Power.
Diffstat (limited to 'riscV')
-rw-r--r--riscV/Archi.v5
1 files changed, 5 insertions, 0 deletions
diff --git a/riscV/Archi.v b/riscV/Archi.v
index e4078132..61d129d0 100644
--- a/riscV/Archi.v
+++ b/riscV/Archi.v
@@ -57,11 +57,16 @@ Lemma choose_nan_32_idem: forall n,
choose_nan_32 (n :: n :: nil) = choose_nan_32 (n :: nil).
Proof. auto. Qed.
+Definition fma_order {A: Type} (x y z: A) := (x, y, z).
+
+Definition fma_invalid_mul_is_nan := false.
+
Definition float_of_single_preserves_sNaN := false.
Global Opaque ptr64 big_endian splitlong
default_nan_64 choose_nan_64
default_nan_32 choose_nan_32
+ fma_order fma_invalid_mul_is_nan
float_of_single_preserves_sNaN.
(** Whether to generate position-independent code or not *)