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-rw-r--r--verilog/Builtins1.v17
1 files changed, 9 insertions, 8 deletions
diff --git a/verilog/Builtins1.v b/verilog/Builtins1.v
index f1d60961..7c77a488 100644
--- a/verilog/Builtins1.v
+++ b/verilog/Builtins1.v
@@ -6,10 +6,11 @@
(* *)
(* Copyright Institut National de Recherche en Informatique et en *)
(* Automatique. All rights reserved. This file is distributed *)
-(* under the terms of the GNU General Public License as published by *)
-(* the Free Software Foundation, either version 2 of the License, or *)
-(* (at your option) any later version. This file is also distributed *)
-(* under the terms of the INRIA Non-Commercial License Agreement. *)
+(* under the terms of the GNU Lesser General Public License as *)
+(* published by the Free Software Foundation, either version 2.1 of *)
+(* the License, or (at your option) any later version. *)
+(* This file is also distributed under the terms of the *)
+(* INRIA Non-Commercial License Agreement. *)
(* *)
(* *********************************************************************)
@@ -41,14 +42,14 @@ Definition platform_builtin_sem (b: platform_builtin) : builtin_sem (sig_res (pl
| BI_fmin =>
mkbuiltin_n2t Tfloat Tfloat Tfloat
(fun f1 f2 => match Float.compare f1 f2 with
- | Some Eq | Some Lt => f1
- | Some Gt | None => f2
+ | Some Lt => f1
+ | Some Eq | Some Gt | None => f2
end)
| BI_fmax =>
mkbuiltin_n2t Tfloat Tfloat Tfloat
(fun f1 f2 => match Float.compare f1 f2 with
- | Some Eq | Some Gt => f1
- | Some Lt | None => f2
+ | Some Gt => f1
+ | Some Eq | Some Lt | None => f2
end)
end.