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| author | Maciej T. Nowak <maciejt.nowak@gmail.com> | 2020-01-03 21:57:19 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-03 21:57:19 +0100 |
| commit | 0201e8ff02b1a789ef603aafe3dab05acadaede5 (patch) | |
| tree | a84952b0cab1d5253573bf0ca18501c8107a9ac3 | |
| parent | e308982e18fc952a8d446ddb7ea8b70433a998c2 (diff) | |
| download | picorv32-0201e8ff02b1a789ef603aafe3dab05acadaede5.tar.gz picorv32-0201e8ff02b1a789ef603aafe3dab05acadaede5.zip | |
spimemio documentation: read latency reset value
According to https://github.com/cliffordwolf/picorv32/blob/c06ba38113b98b4996aed6d523667444a5d83bf6/picosoc/spimemio.v#L111 the reset value for `Read latency (dummy) cycles` is 8 cycles, not 0.
| -rw-r--r-- | picosoc/README.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index 4d02128..9c26f14 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -75,7 +75,7 @@ mapped to the low byte of the 32 bit word at address 0x03000000. | 22 | DDR Enable bit (reset=0) | | 21 | QSPI Enable bit (reset=0) | | 20 | CRM Enable bit (reset=0) | -| 19:16 | Read latency (dummy) cycles (reset=0) | +| 19:16 | Read latency (dummy) cycles (reset=8) | | 15:12 | Reserved (read 0) | | 11:8 | IO Output enable bits in bit bang mode | | 7:6 | Reserved (read 0) | |