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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-27 10:18:30 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-27 10:18:30 +0100 |
| commit | 0b8795443744ee9727d4e5c4c4e3f2b3348b3702 (patch) | |
| tree | 53ebc6dbc927e9edd6bbc774571297462cda40d0 | |
| parent | 1d9f5b7678c008fd4ab71d9c742a70ff2365f186 (diff) | |
| download | picorv32-0b8795443744ee9727d4e5c4c4e3f2b3348b3702.tar.gz picorv32-0b8795443744ee9727d4e5c4c4e3f2b3348b3702.zip | |
Fix simulation
| -rw-r--r-- | picosoc/Makefile | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/picosoc/Makefile b/picosoc/Makefile index 9c80745..291a12d 100644 --- a/picosoc/Makefile +++ b/picosoc/Makefile @@ -14,13 +14,13 @@ hx8kdemo.json: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^ hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS -hx8kdemo_syn.v: hx8kdemo.blif - yosys -p 'read_blif -wideports hx8kdemo.blif; write_verilog hx8kdemo_syn.v' +hx8kdemo_syn.v: hx8kdemo.json + yosys -p 'read_json hx8kdemo.json; write_verilog hx8kdemo_syn.v' hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.json nextpnr-ice40 --hx8k --package ct256 --asc hx8kdemo.asc --json hx8kdemo.json --pcf hx8kdemo.pcf @@ -60,10 +60,10 @@ icebreaker.json: icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc. yosys -ql icebreaker.log -p 'synth_ice40 -dsp -top icebreaker -json icebreaker.json' $^ icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS icebreaker_syn.v: icebreaker.json yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v' @@ -96,8 +96,8 @@ icebreaker_fw.bin: icebreaker_fw.elf # ---- Testbench for SPI Flash Model ---- -spiflash_tb: spiflash_tb.vvp firmware.hex - vvp -N $< +spiflash_tb: spiflash_tb.vvp icebreaker_fw.hex + vvp -N $< +firmware=icebreaker_fw.hex spiflash_tb.vvp: spiflash.v spiflash_tb.v iverilog -s testbench -o $@ $^ |