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| author | Clifford Wolf <clifford@clifford.at> | 2018-09-30 14:27:17 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-09-30 14:27:17 +0200 |
| commit | 0d573311ce081a1eb4f4bbed69a8f4b2de4d656a (patch) | |
| tree | 99d5041e29c7a7c6cc78146855fc1f1d62018f5d | |
| parent | 028aa757dfdf1c4ed667cea5dec3c30d22bcd36e (diff) | |
| parent | e507c54058598f51f47c3a487bc6025dc9d6c630 (diff) | |
| download | picorv32-0d573311ce081a1eb4f4bbed69a8f4b2de4d656a.tar.gz picorv32-0d573311ce081a1eb4f4bbed69a8f4b2de4d656a.zip | |
Merge pull request #89 from emilio93/patch-1
Update Risc-V website link for tools
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -6,7 +6,7 @@ PicoRV32 is a CPU core that implements the [RISC-V RV32IMC Instruction Set](http It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. -Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools). +Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](https://riscv.org/software-status/). The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in `/opt/riscv32i[m][c]`. See the [build instructions below](#building-a-pure-rv32i-toolchain) for details. |