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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-29 07:37:48 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-29 07:37:48 +0200 |
| commit | 1321840665044252623a78d1a6b32d12d26833bf (patch) | |
| tree | 310ec325606dbae15c419f070afcaab82eaa8e68 | |
| parent | 46026ba985d1ffb062802651d99ae34d5b1f773d (diff) | |
| download | picorv32-1321840665044252623a78d1a6b32d12d26833bf.tar.gz picorv32-1321840665044252623a78d1a6b32d12d26833bf.zip | |
Minor README change
| -rw-r--r-- | README.md | 7 |
1 files changed, 6 insertions, 1 deletions
@@ -153,7 +153,8 @@ interface only becomes functional when ENABLE_PCPI is set as well. #### ENABLE_IRQ (default = 0) -Set this to 1 to enable IRQs. (see "" below for a discussion of IRQs) +Set this to 1 to enable IRQs. (see "Custom Instructions for IRQ Handling" below +for a discussion of IRQs) #### ENABLE_IRQ_QREGS (default = 1) @@ -163,10 +164,14 @@ bitmask in x4 (tp), the global pointer and thread pointer registers according to the RISC-V ABI. Code generated from ordinary C code will not interact with those registers. +Support for q-registers is always disabled when ENABLE_IRQ is set to 0. + #### ENABLE_IRQ_TIMER (default = 1) Set this to 0 to disable support for the `timer` instruction. +Support for the timer is always disabled when ENABLE_IRQ is set to 0. + #### MASKED_IRQ (default = 32'h 0000_0000) A 1 bit in this bitmask corresponds to a permanently disabled IRQ. |