- fix missed timer interrupts,

  when another interrupt activates shortly before

1 files changed, 7 insertions, 6 deletions

diff --git a/picorv32.v b/picorv32.v
index 62e7770..4b1eca9 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -1435,15 +1435,9 @@ module picorv32 #(
 		next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
 
 		if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
-			if (timer - 1 == 0)
-				next_irq_pending[irq_timer] = 1;
 			timer <= timer - 1;
 		end
 
-		if (ENABLE_IRQ) begin
-			next_irq_pending = next_irq_pending | irq;
-		end
-
 		decoder_trigger <= mem_do_rinst && mem_done;
 		decoder_trigger_q <= decoder_trigger;
 		decoder_pseudo_trigger <= 0;
@@ -1913,6 +1907,13 @@ module picorv32 #(
 			end
 		endcase
 
+		if (ENABLE_IRQ) begin
+			next_irq_pending = next_irq_pending | irq;
+			if ENABLE_IRQ_TIMER && timer
+				if (timer - 1 == 0)
+					next_irq_pending[irq_timer] = 1;
+		end
+
 		if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
 			if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
 				`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)