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| author | Clifford Wolf <clifford@clifford.at> | 2016-01-21 11:39:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-01-21 11:39:24 +0100 |
| commit | 56ea35cc222413f3bb9ba06927a20c714af86a25 (patch) | |
| tree | b80cfcd7d98b35c348375f42ee107136e4abf80e | |
| parent | d2e20edaab27d6891294dd3c2aadf871c874d431 (diff) | |
| download | picorv32-56ea35cc222413f3bb9ba06927a20c714af86a25.tar.gz picorv32-56ea35cc222413f3bb9ba06927a20c714af86a25.zip | |
Updated riscv-gnu-toolchain
| -rw-r--r-- | README.md | 16 |
1 files changed, 8 insertions, 8 deletions
@@ -257,10 +257,10 @@ Unless stated otherwise, the following numbers apply to a PicoRV32 with ENABLE_REGS_DUALPORT active and connected to a memory that can accommodate requests within one clock cycle. -The average Cycles per Instruction (CPI) is 4 to 5, depending on the mix of -instructions in the code. The CPI numbers for the individual instructions -can be found in the table below. The column "CPI (SP)" contains the -CPI numbers for a core built without ENABLE_REGS_DUALPORT. +The average Cycles per Instruction (CPI) is approximately 4, depending on the mix of +instructions in the code. The CPI numbers for the individual instructions can +be found in the table below. The column "CPI (SP)" contains the CPI numbers for +a core built without ENABLE_REGS_DUALPORT. | Instruction | CPI | CPI (SP) | | ---------------------| ----:| --------:| @@ -277,9 +277,9 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT. When `ENABLE_MUL` is activated, then a `MUL` instruction will execute in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles. -Dhrystone benchmark results: 0.311 DMIPS/MHz (547 Dhrystones/Second/MHz) +Dhrystone benchmark results: 0.327 DMIPS/MHz (575 Dhrystones/Second/MHz) -For the Dhrystone benchmark the average CPI is 4.144. +For the Dhrystone benchmark the average CPI is 3.945. PicoRV32 Native Memory Interface @@ -531,7 +531,7 @@ pure RV32I target, and install it in `/opt/riscv32i`: git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i cd riscv-gnu-toolchain-rv32i - git checkout 4bcd4f5 + git checkout 06c957a mkdir build; cd build ../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i @@ -541,7 +541,7 @@ The commands will all be named using the prefix `riscv32-unknown-elf-`, which makes it easy to install them side-by-side with the regular riscv-tools, which are using the name prefix `riscv64-unknown-elf-` by default. -*Note: This instructions are for git rev 4bcd4f5 (2015-12-14) of riscv-gnu-toolchain.* +*Note: This instructions are for git rev 06c957a (2016-01-20) of riscv-gnu-toolchain.* Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs |