Using .vvp instead of .exe for iverilog executables

8 files changed, 76 insertions, 77 deletions

diff --git a/.gitignore b/.gitignore
index a9d7413..846b1a5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,9 +8,9 @@
 /dhrystone/dhry.elf
 /dhrystone/dhry.hex
 /dhrystone/dhry.map
-/dhrystone/testbench.exe
+/dhrystone/testbench.vvp
 /dhrystone/testbench.vcd
-/dhrystone/timing.exe
+/dhrystone/timing.vvp
 /dhrystone/timing.txt
 /dhrystone/*.d
 /dhrystone/*.o
@@ -18,10 +18,9 @@
 /riscv-gnu-toolchain-riscv32ic
 /riscv-gnu-toolchain-riscv32im
 /riscv-gnu-toolchain-riscv32imc
-/testbench.exe
-/testbench_sp.exe
-/testbench_axi.exe
-/testbench_synth.exe
+/testbench.vvp
+/testbench_sp.vvp
+/testbench_synth.vvp
 /testbench.gtkw
 /testbench.vcd
 /check.smt2
diff --git a/Makefile b/Makefile
index 02c86d5..4d5d7b5 100644
--- a/Makefile
+++ b/Makefile
@@ -11,10 +11,10 @@ GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedanti
 TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
 COMPRESSED_ISA = C
 
-test: testbench.exe firmware/firmware.hex
-	vvp -N testbench.exe
+test: testbench.vvp firmware/firmware.hex
+	vvp -N testbench.vvp
 
-testbench.vcd: testbench.exe firmware/firmware.hex
+testbench.vcd: testbench.vvp firmware/firmware.hex
 	vvp -N $< +vcd
 
 view: testbench.vcd
@@ -29,26 +29,26 @@ check.smt2: picorv32.v
 	          -p 'prep -top picorv32 -nordff' \
 		  -p 'write_smt2 -bv -mem -wires check.smt2'
 
-test_sp: testbench_sp.exe firmware/firmware.hex
-	vvp -N testbench_sp.exe
+test_sp: testbench_sp.vvp firmware/firmware.hex
+	vvp -N testbench_sp.vvp
 
-test_axi: testbench.exe firmware/firmware.hex
-	vvp -N testbench.exe +axi_test
+test_axi: testbench.vvp firmware/firmware.hex
+	vvp -N testbench.vvp +axi_test
 
-test_synth: testbench_synth.exe firmware/firmware.hex
-	vvp -N testbench_synth.exe
+test_synth: testbench_synth.vvp firmware/firmware.hex
+	vvp -N testbench_synth.vvp
 
-testbench.exe: testbench.v picorv32.v
-	iverilog -o testbench.exe $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) testbench.v picorv32.v
-	chmod -x testbench.exe
+testbench.vvp: testbench.v picorv32.v
+	iverilog -o testbench.vvp $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) testbench.v picorv32.v
+	chmod -x testbench.vvp
 
-testbench_sp.exe: testbench.v picorv32.v
-	iverilog -o testbench_sp.exe $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST testbench.v picorv32.v
-	chmod -x testbench_sp.exe
+testbench_sp.vvp: testbench.v picorv32.v
+	iverilog -o testbench_sp.vvp $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST testbench.v picorv32.v
+	chmod -x testbench_sp.vvp
 
-testbench_synth.exe: testbench.v synth.v
-	iverilog -o testbench_synth.exe testbench.v synth.v
-	chmod -x testbench_synth.exe
+testbench_synth.vvp: testbench.v synth.v
+	iverilog -o testbench_synth.vvp testbench.v synth.v
+	chmod -x testbench_synth.vvp
 
 synth.v: picorv32.v scripts/yosys/synth_sim.ys
 	yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
@@ -119,7 +119,7 @@ clean:
 		riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc
 	rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
 		firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
-		testbench.exe testbench_sp.exe testbench_synth.exe testbench.vcd
+		testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench.vcd
 
 .PHONY: test view test_sp test_axi test_synth download-tools toc clean
 
diff --git a/dhrystone/Makefile b/dhrystone/Makefile
index 707a94f..255749d 100644
--- a/dhrystone/Makefile
+++ b/dhrystone/Makefile
@@ -3,23 +3,23 @@ OBJS = start.o dhry_1.o dhry_2.o stdlib.o
 CFLAGS = -MD -O3 -m32 -march=RV32IM -ffreestanding -nostdlib -DTIME -DRISCV
 TOOLCHAIN_PREFIX = riscv32-unknown-elf-
 
-test: testbench.exe dhry.hex
-	vvp -N testbench.exe
+test: testbench.vvp dhry.hex
+	vvp -N testbench.vvp
 
 timing: timing.txt
 	grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \
 		gawk '{printf("%03d-%-7s %2d %-8s (%d)\n",$$3,$$2,$$3,$$2,$$1);}' | sort | cut -c13-
 
-timing.txt: timing.exe dhry.hex
-	vvp -N timing.exe > timing.txt
+timing.txt: timing.vvp dhry.hex
+	vvp -N timing.vvp > timing.txt
 
-testbench.exe: testbench.v ../picorv32.v
-	iverilog -o testbench.exe testbench.v ../picorv32.v
-	chmod -x testbench.exe
+testbench.vvp: testbench.v ../picorv32.v
+	iverilog -o testbench.vvp testbench.v ../picorv32.v
+	chmod -x testbench.vvp
 
-timing.exe: testbench.v ../picorv32.v
-	iverilog -o timing.exe -DTIMING testbench.v ../picorv32.v
-	chmod -x timing.exe
+timing.vvp: testbench.v ../picorv32.v
+	iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v
+	chmod -x timing.vvp
 
 dhry.hex: dhry.bin ../firmware/makehex.py
 	python3 ../firmware/makehex.py $< 16384 > $@
@@ -41,7 +41,7 @@ dhry.elf: $(OBJS) ../firmware/sections.lds
 dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
 
 clean:
-	rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd timing.exe timing.txt
+	rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt
 
 .PHONY: test clean
 
diff --git a/scripts/csmith/.gitignore b/scripts/csmith/.gitignore
index 3441391..646c095 100644
--- a/scripts/csmith/.gitignore
+++ b/scripts/csmith/.gitignore
@@ -6,7 +6,7 @@ platform.info
 test.c
 test.ld
 test.elf
-test.exe
+test_ref
 test.hex
-testbench.exe
+testbench.vvp
 testbench.vcd
diff --git a/scripts/csmith/Makefile b/scripts/csmith/Makefile
index e3cbbd7..4fd060b 100644
--- a/scripts/csmith/Makefile
+++ b/scripts/csmith/Makefile
@@ -3,9 +3,9 @@ RISCV_TOOLS_PREFIX = $(RISCV_TOOLS_DIR)/bin/riscv32-unknown-elf-
 CSMITH_INCDIR = $(shell ls -d /usr/local/include/csmith-* | head -n1)
 CC = $(RISCV_TOOLS_PREFIX)gcc
 
-run: test.exe test.hex testbench.exe
-	./test.exe | tee output_ref.txt
-	vvp -N testbench.exe | tee output_sim.txt
+run: test_ref test.hex testbench.vvp
+	./test_ref | tee output_ref.txt
+	vvp -N testbench.vvp | tee output_sim.txt
 	diff -u output_ref.txt output_sim.txt
 
 spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test.elf
@@ -24,9 +24,9 @@ riscv-isa-sim/build.ok: riscv-fesvr/build.ok
 	cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC
 	+cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok
 
-testbench.exe: testbench.v ../../picorv32.v
-	iverilog -o testbench.exe testbench.v ../../picorv32.v
-	chmod -x testbench.exe
+testbench.vvp: testbench.v ../../picorv32.v
+	iverilog -o testbench.vvp testbench.v ../../picorv32.v
+	chmod -x testbench.vvp
 
 test.hex: test.elf
 	$(RISCV_TOOLS_PREFIX)objcopy -O verilog test.elf test.hex
@@ -35,8 +35,8 @@ start.elf: start.S start.ld
 	$(CC) -nostdlib -o start.elf start.S -T start.ld
 	chmod -x start.elf
 
-test.exe: test.c
-	gcc -m32 -o test.exe -w -Os -I $(CSMITH_INCDIR) test.c
+test_ref: test.c
+	gcc -m32 -o test_ref -w -Os -I $(CSMITH_INCDIR) test.c
 
 test.elf: test.c syscalls.c start.S
 	sed -e '/SECTIONS/,+1 s/{/{ . = 0x00000000; .start : { *(.text.start) } application_entry_point = 0x00010000;/;' \
@@ -50,8 +50,8 @@ test.c:
 	csmith -o test.c
 
 clean:
-	rm -f platform.info test.c test.ld test.elf test.hex test.exe
-	rm -f testbench.exe testbench.vcd output_ref.txt output_sim.txt
+	rm -f platform.info test.c test.ld test.elf test.hex test_ref
+	rm -f testbench.vvp testbench.vcd output_ref.txt output_sim.txt
 
 mrproper: clean
 	rm -rf riscv-fesvr riscv-isa-sim
diff --git a/scripts/cxxdemo/.gitignore b/scripts/cxxdemo/.gitignore
index 563b908..47e6b5c 100644
--- a/scripts/cxxdemo/.gitignore
+++ b/scripts/cxxdemo/.gitignore
@@ -4,6 +4,6 @@ firmware.hex
 firmware32.hex
 firmware.o
 syscalls.o
-testbench.exe
+testbench.vvp
 testbench.vcd
 start.elf
diff --git a/scripts/cxxdemo/Makefile b/scripts/cxxdemo/Makefile
index d811427..e858761 100644
--- a/scripts/cxxdemo/Makefile
+++ b/scripts/cxxdemo/Makefile
@@ -7,12 +7,12 @@ CCFLAGS = -MD -Os -Wall -std=c++11
 LDFLAGS = -Wl,--gc-sections
 LDLIBS = -lstdc++
 
-test: testbench.exe firmware32.hex
-	vvp -N testbench.exe
+test: testbench.vvp firmware32.hex
+	vvp -N testbench.vvp
 
-testbench.exe: testbench.v ../../picorv32.v
-	iverilog -o testbench.exe testbench.v ../../picorv32.v
-	chmod -x testbench.exe
+testbench.vvp: testbench.v ../../picorv32.v
+	iverilog -o testbench.vvp testbench.v ../../picorv32.v
+	chmod -x testbench.vvp
 
 firmware32.hex: firmware.elf start.elf hex8tohex32.py
 	$(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp
@@ -32,7 +32,7 @@ start.elf: start.S start.ld
 clean:
 	rm -f *.o *.d *.tmp start.elf
 	rm -f firmware.elf firmware.hex firmware32.hex
-	rm -f testbench.exe testbench.vcd
+	rm -f testbench.vvp testbench.vcd
 
 -include *.d
 .PHONY: test clean
diff --git a/scripts/icestorm/Makefile b/scripts/icestorm/Makefile
index 8f70913..74ba34d 100644
--- a/scripts/icestorm/Makefile
+++ b/scripts/icestorm/Makefile
@@ -24,38 +24,38 @@ example.txt: synth.blif
 example.bin: example.txt
 	icepack example.txt example.bin
 
-example_tb.exe: example_tb.v example.v firmware.hex
-	iverilog -o example_tb.exe -s testbench example.v example_tb.v ../../picorv32.v
-	chmod -x example_tb.exe
+example_tb.vvp: example_tb.v example.v firmware.hex
+	iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v
+	chmod -x example_tb.vvp
 
-example_sim: example_tb.exe
-	vvp -N example_tb.exe
+example_sim: example_tb.vvp
+	vvp -N example_tb.vvp
 
-example_sim_vcd: example_tb.exe
-	vvp -N example_tb.exe +vcd
+example_sim_vcd: example_tb.vvp
+	vvp -N example_tb.vvp +vcd
 
-synth_tb.exe: example_tb.v synth.blif
-	iverilog -o synth_tb.exe -s testbench synth.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
-	chmod -x synth_tb.exe
+synth_tb.vvp: example_tb.v synth.blif
+	iverilog -o synth_tb.vvp -s testbench synth.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
+	chmod -x synth_tb.vvp
 
-synth_sim: synth_tb.exe
-	vvp -N synth_tb.exe
+synth_sim: synth_tb.vvp
+	vvp -N synth_tb.vvp
 
-synth_sim_vcd: synth_tb.exe
-	vvp -N synth_tb.exe +vcd
+synth_sim_vcd: synth_tb.vvp
+	vvp -N synth_tb.vvp +vcd
 
 route.v: example.txt
 	icebox_vlog -L -n top -sp example.pcf example.txt > route.v
 
-route_tb.exe: example_tb.v route.v
-	iverilog -o route_tb.exe -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
-	chmod -x route_tb.exe
+route_tb.vvp: example_tb.v route.v
+	iverilog -o route_tb.vvp -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
+	chmod -x route_tb.vvp
 
-route_sim: route_tb.exe
-	vvp -N route_tb.exe
+route_sim: route_tb.vvp
+	vvp -N route_tb.vvp
 
-route_sim_vcd: route_tb.exe
-	vvp -N route_tb.exe +vcd
+route_sim_vcd: route_tb.vvp
+	vvp -N route_tb.vvp +vcd
 
 prog_sram:
 	iceprog -S example.bin
@@ -66,7 +66,7 @@ view:
 clean:
 	rm -f firmware.elf firmware.map firmware.bin firmware.hex
 	rm -f synth.log synth.v synth.blif route.v example.txt example.bin
-	rm -f example_tb.exe synth_tb.exe route_tb.exe example.vcd
+	rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
 
 .PHONY: all prog_sram view clean
 .PHONY: example_sim synth_sim route_sim