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author | Claire Wolf <clifford@clifford.at> | 2020-04-15 18:49:23 +0200 |
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committer | GitHub <noreply@github.com> | 2020-04-15 18:49:23 +0200 |
commit | 824a5c801194299f89f4fd8844c1fbcd1bdf4e21 (patch) | |
tree | 68a497ebdf1742cf3997587d3449565f4e97d4f7 | |
parent | e308982e18fc952a8d446ddb7ea8b70433a998c2 (diff) | |
parent | a7ff70dfb44cf127a318c6c70497a503fa7002a7 (diff) | |
download | picorv32-824a5c801194299f89f4fd8844c1fbcd1bdf4e21.tar.gz picorv32-824a5c801194299f89f4fd8844c1fbcd1bdf4e21.zip |
Merge pull request #158 from rxrbln/uart
added default clk divider parameter to simpleuart
-rw-r--r-- | picosoc/simpleuart.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/picosoc/simpleuart.v b/picosoc/simpleuart.v index 50808cb..1efddef 100644 --- a/picosoc/simpleuart.v +++ b/picosoc/simpleuart.v @@ -17,7 +17,7 @@ * */ -module simpleuart ( +module simpleuart #(parameter integer DEFAULT_DIV = 1) ( input clk, input resetn, @@ -54,7 +54,7 @@ module simpleuart ( always @(posedge clk) begin if (!resetn) begin - cfg_divider <= 1; + cfg_divider <= DEFAULT_DIV; end else begin if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0]; if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8]; |