Added STACKADDR parameter

2 files changed, 15 insertions, 1 deletions

diff --git a/README.md b/README.md
index 266eea1..a01d330 100644
--- a/README.md
+++ b/README.md
@@ -279,6 +279,14 @@ The start address of the program.
 
 The start address of the interrupt handler.
 
+#### STACKADDR (default = 32'h ffff_ffff)
+
+When this parameter has a value different from 0xffffffff, then register `x2` (the
+stack pointer) is initialized to this value on reset. (All other registers remain
+uninitialized.) Note that the RISC-V calling convention requires the stack pointer
+to be aligned on 16 bytes boundaries (4 bytes for the RV32I soft float calling
+convention).
+
 
 Cycles per Instruction Performance
 ----------------------------------
diff --git a/picorv32.v b/picorv32.v
index 755bc04..2da99fd 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -61,7 +61,8 @@ module picorv32 #(
 	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
 	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
 	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
-	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
 ) (
 	input clk, resetn,
 	output reg trap,
@@ -1162,6 +1163,11 @@ module picorv32 #(
 			irq_state <= 0;
 			eoi <= 0;
 			timer <= 0;
+			if (~STACKADDR) begin
+				latched_store <= 1;
+				latched_rd <= 2;
+				reg_out <= STACKADDR;
+			end
 			cpu_state <= cpu_state_fetch;
 		end else
 		(* parallel_case, full_case *)