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| author | Claire Xen <claire@clairexen.net> | 2022-01-03 16:03:13 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-03 16:03:13 +0100 |
| commit | f00a88c36eaab478b64ee27d8162e421049bcc66 (patch) | |
| tree | 7d604206a2deb29c9f097ff1f3b7de78f44b34a3 | |
| parent | 1d9f5b7678c008fd4ab71d9c742a70ff2365f186 (diff) | |
| parent | e8dbd9ac6a28094b9a2c04cb79478d68b0e3eb07 (diff) | |
| download | picorv32-f00a88c36eaab478b64ee27d8162e421049bcc66.tar.gz picorv32-f00a88c36eaab478b64ee27d8162e421049bcc66.zip | |
Cleanups
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | dhrystone/Makefile | 2 | ||||
| -rw-r--r-- | dhrystone/dhry.h | 5 | ||||
| -rw-r--r-- | picosoc/.gitignore | 2 | ||||
| -rw-r--r-- | picosoc/Makefile | 16 |
5 files changed, 16 insertions, 11 deletions
@@ -93,7 +93,7 @@ check-%: check.smt2 check.smt2: picorv32.v yosys -v2 -p 'read_verilog -formal picorv32.v' \ -p 'prep -top picorv32 -nordff' \ - -p 'assertpmux -noinit; opt -fast' \ + -p 'assertpmux -noinit; opt -fast; dffunmap' \ -p 'write_smt2 -wires check.smt2' synth.v: picorv32.v scripts/yosys/synth_sim.ys diff --git a/dhrystone/Makefile b/dhrystone/Makefile index 4dc0361..89cb110 100644 --- a/dhrystone/Makefile +++ b/dhrystone/Makefile @@ -1,6 +1,6 @@ USE_MYSTDLIB = 0 OBJS = dhry_1.o dhry_2.o stdlib.o -CFLAGS = -MD -O3 -march=rv32im -DTIME -DRISCV +CFLAGS = -MD -O3 -mabi=ilp32 -march=rv32im -DTIME -DRISCV TOOLCHAIN_PREFIX = /opt/riscv32im/bin/riscv32-unknown-elf- ifeq ($(USE_MYSTDLIB),1) diff --git a/dhrystone/dhry.h b/dhrystone/dhry.h index bafacc6..41f1495 100644 --- a/dhrystone/dhry.h +++ b/dhrystone/dhry.h @@ -383,8 +383,13 @@ /* General definitions: */ +#ifdef USE_MYSTDLIB +extern char *strcpy(char *dest, const char *src); +extern int strcmp(const char *s1, const char *s2); +#else #include <stdio.h> /* for strcpy, strcmp */ +#endif #define Null 0 /* Value of a Null pointer */ diff --git a/picosoc/.gitignore b/picosoc/.gitignore index 08067d3..4ac8239 100644 --- a/picosoc/.gitignore +++ b/picosoc/.gitignore @@ -2,7 +2,7 @@ /spiflash_tb.vvp /hx8kdemo.asc /hx8kdemo.bin -/hx8kdemo.blif +/hx8kdemo.json /hx8kdemo.log /hx8kdemo.rpt /hx8kdemo_syn.v diff --git a/picosoc/Makefile b/picosoc/Makefile index 9c80745..291a12d 100644 --- a/picosoc/Makefile +++ b/picosoc/Makefile @@ -14,13 +14,13 @@ hx8kdemo.json: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^ hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS -hx8kdemo_syn.v: hx8kdemo.blif - yosys -p 'read_blif -wideports hx8kdemo.blif; write_verilog hx8kdemo_syn.v' +hx8kdemo_syn.v: hx8kdemo.json + yosys -p 'read_json hx8kdemo.json; write_verilog hx8kdemo_syn.v' hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.json nextpnr-ice40 --hx8k --package ct256 --asc hx8kdemo.asc --json hx8kdemo.json --pcf hx8kdemo.pcf @@ -60,10 +60,10 @@ icebreaker.json: icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc. yosys -ql icebreaker.log -p 'synth_ice40 -dsp -top icebreaker -json icebreaker.json' $^ icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v - iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS icebreaker_syn.v: icebreaker.json yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v' @@ -96,8 +96,8 @@ icebreaker_fw.bin: icebreaker_fw.elf # ---- Testbench for SPI Flash Model ---- -spiflash_tb: spiflash_tb.vvp firmware.hex - vvp -N $< +spiflash_tb: spiflash_tb.vvp icebreaker_fw.hex + vvp -N $< +firmware=icebreaker_fw.hex spiflash_tb.vvp: spiflash.v spiflash_tb.v iverilog -s testbench -o $@ $^ |