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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-29 16:09:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-29 16:09:29 +0200 |
| commit | fdb2e5feb53114f46ec31a970bf6f4a4d63c543d (patch) | |
| tree | 06a5839af8627a13475bc5c782b68a5dc4935b4b | |
| parent | 098829e5791abc5aaa641d423eb278ffb306f70a (diff) | |
| download | picorv32-fdb2e5feb53114f46ec31a970bf6f4a4d63c543d.tar.gz picorv32-fdb2e5feb53114f46ec31a970bf6f4a4d63c543d.zip | |
Update spiflash README
| -rw-r--r-- | spiflash/README | 18 | ||||
| -rw-r--r-- | spiflash/README.md | 27 |
2 files changed, 27 insertions, 18 deletions
diff --git a/spiflash/README b/spiflash/README deleted file mode 100644 index 753458b..0000000 --- a/spiflash/README +++ /dev/null @@ -1,18 +0,0 @@ - -PicoRV32 SPI-Flash Demo -======================= - -This is a simple PicoRV32 example design that can run code directly from an SPI -flash chip. This example design uses the Lattice iCE40-HX8K Breakout Board. - -The flash is mapped to the memory region starting at 0x80000000. The reset -vector is set to 0x80100000, i.e. at the 1MB offset inside the flash memory. - -A small scratchpad memory (default 256 words, i.e. 1 kB) is mapped to address -0x00000000. A simple GPIO controller is mapped to address 0xC0000000. - -Run "make test" to run the test bench (and create testbench.vcd). - -Run "make prog" to build the configuration bit-stream and firmware images -and upload them to a connected iCE40-HX8K Breakout Board. - diff --git a/spiflash/README.md b/spiflash/README.md new file mode 100644 index 0000000..e141ea2 --- /dev/null +++ b/spiflash/README.md @@ -0,0 +1,27 @@ + +PicoRV32 SPI-Flash Demo +======================= + +This is a simple PicoRV32 example design that can run code directly from an SPI +flash chip. This example design uses the Lattice iCE40-HX8K Breakout Board. + +The flash is mapped to the memory region starting at 0x80000000. The reset +vector is set to 0x80100000, i.e. at the 1MB offset inside the flash memory. + +A small scratchpad memory (default 256 words, i.e. 1 kB) is mapped to address +0x00000000. A simple GPIO controller is mapped to address 0xC0000000. + +Run `make test` to run the test bench (and create `testbench.vcd`). + +Run `make prog` to build the configuration bit-stream and firmware images +and upload them to a connected iCE40-HX8K Breakout Board. + +| File | Description | +| --------------------------- | --------------------------------------------------------------- | +| [top.v](top.v) | Top-level Verilog module for the design | +| [spimemio.v](spimemio.v) | Memory controller that interfaces to external SPI flash | +| [spiflash.v](spiflash.v) | Simulation model of an SPI flash (used by testbench.v) | +| [testbench.v](testbench.v) | Simple test bench for the design (requires firmware.hex). | +| [firmware.s](firmware.s) | Assembler source for firmware.hex/firmware.bin. | +| [pinout.pcf](pinout.pcf) | Pin constraints for implementation on iCE40-HX8K Breakout Board | + |