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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-28 13:07:50 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-28 13:07:50 +0200 |
| commit | 1f99de511760b3acb546e62623c65d6143b30a77 (patch) | |
| tree | b5bc87d754052c1cbd10005e8dd794ab4528eb23 /README.md | |
| parent | 923ac360ff3dfd4fccb4e40dcd32c9f560a8afa1 (diff) | |
| download | picorv32-1f99de511760b3acb546e62623c65d6143b30a77.tar.gz picorv32-1f99de511760b3acb546e62623c65d6143b30a77.zip | |
Improvements in picorv32_pcpi_mul
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -194,6 +194,9 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT. | indirect jump (jalr) | 6 | 6 | | shift operations | 4-14 | 4-15 | +When `ENABLE_MUL` is activated, then a `MUL` instruction will execute +in 42 cycles and a `MULH[SU|U]` instruction will execute in 74 cycles. + Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz) For the Dhrystone benchmark the average CPI is 4.167. |