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| author | Clifford Wolf <clifford@clifford.at> | 2015-11-03 18:59:12 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-11-03 18:59:12 +0100 |
| commit | 8d9f048785a4972fee5817cc64ddb2097034b122 (patch) | |
| tree | 5a227d5ab158f7424683a02ee741d3cd36a4a1f9 /README.md | |
| parent | 17a665913ef2bf740e8ba03af05f58a978d52e77 (diff) | |
| download | picorv32-8d9f048785a4972fee5817cc64ddb2097034b122.tar.gz picorv32-8d9f048785a4972fee5817cc64ddb2097034b122.zip | |
Using riscv32-unknown-elf- toolchain
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -5,6 +5,8 @@ PicoRV32 - A Size-Optimized RISC-V CPU PicoRV32 is a CPU core that implements the [RISC-V RV32I Instruction Set](http://riscv.org/). Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools). +The examples bundled with PicoRV32 (such as the firmware for `make test`) expect a `riscv32-unknown-elf-` toolchain +(see [build instructions below](#building-a-pure-rv32i-toolchain)) installed in `$PATH`. PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license) (a license that is similar in terms to the MIT license or the 2-clause BSD license). |