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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-26 14:54:27 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-26 14:54:27 +0200 |
| commit | 98d248d2c2f785f1b35ce7a08df7705e1945597f (patch) | |
| tree | 67560a9a31fd39220d27c6bef2afd665dc50e59a /README.md | |
| parent | 7094e61af7dfe3c24ff4218557b209a1b09e5793 (diff) | |
| download | picorv32-98d248d2c2f785f1b35ce7a08df7705e1945597f.tar.gz picorv32-98d248d2c2f785f1b35ce7a08df7705e1945597f.zip | |
Finalized tracer support
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -256,6 +256,13 @@ Set this to 0 to disable support for the `timer` instruction. Support for the timer is always disabled when ENABLE_IRQ is set to 0. +#### ENABLE_TRACE (default = 0) + +Produce an execution trace using the `trace_valid` and `trace_data` output ports. +For a demontration of this feature run `make testbench.vcd` to create a trace file +and then run `python3 showtrace.py testbench.trace firmware/firmware.elf` to decode +it. + #### REGS_INIT_ZERO (default = 0) Set this to 1 to initialize all registers to zero (using a Verilog `initial` block). |