diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-06-28 14:51:53 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-28 14:51:53 +0200 |
| commit | b076d72806fb84ee0557a75f871aef0ba0d6a66b (patch) | |
| tree | 43b4eee85d025c53654833e284f8cb89b2feb642 /README.md | |
| parent | 094dc690bbd7d1d4a6ffcb74e3385a9dfbb29905 (diff) | |
| download | picorv32-b076d72806fb84ee0557a75f871aef0ba0d6a66b.tar.gz picorv32-b076d72806fb84ee0557a75f871aef0ba0d6a66b.zip | |
Fixed PCPI instr prefetching
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 7 |
1 files changed, 4 insertions, 3 deletions
@@ -195,7 +195,7 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT. | shift operations | 4-14 | 4-15 | When `ENABLE_MUL` is activated, then a `MUL` instruction will execute -in 42 cycles and a `MULH[SU|U]` instruction will execute in 74 cycles. +in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles. Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz) @@ -405,12 +405,13 @@ enabled PCPI, IRQ and MUL features. | PicoRV32 "regular" | 996 | 48 | | PicoRV32 "large" | 1814 | 88 | +*Note: Most of the size reduction in the "small" core comes from eliminating +the counter instructions, not from reducing the size of the register file.* + Todos: ------ -- Optional FENCE support -- Optional write-through cache - Optional support for compressed ISA - Improved documentation and examples |