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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-07 22:51:52 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-07 22:51:52 +0200 |
| commit | b6c4c2eeb9c7c90d5cb60c03f223cffebfec0e8d (patch) | |
| tree | 9da736977cd95fba71b757f7a0d5ada6aaa5da71 /README.md | |
| parent | 54f89ba904011d4ffd3d6a866d91f264a9327be2 (diff) | |
| download | picorv32-b6c4c2eeb9c7c90d5cb60c03f223cffebfec0e8d.tar.gz picorv32-b6c4c2eeb9c7c90d5cb60c03f223cffebfec0e8d.zip | |
Added TWO_CYCLE_COMPARE
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -165,6 +165,12 @@ of 4 bits and then shift in units of 1 bit. This speeds up shift operations, but adds additional hardware. Set this parameter to 0 to disable the two-stage shift to further reduce the size of the core. +#### TWO_CYCLE_COMPARE (default = 0) + +This relaxes the longest data path a bit by adding an additional FF stage +at the cost of adding an additional clock cycle delay to the conditional +branch instructions. + #### CATCH_MISALIGN (default = 1) Set this to 0 to disable the circuitry for catching misaligned memory |