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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-26 16:15:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-26 16:15:39 +0200 |
| commit | f0b824ad9a0d9c4a010baf62114009c847f6a94d (patch) | |
| tree | 90534d18526dac83077132f220e25f25e5db3abf /README.md | |
| parent | c06286423b912bcfbbb10f0c00a00ca9e362ffc3 (diff) | |
| download | picorv32-f0b824ad9a0d9c4a010baf62114009c847f6a94d.tar.gz picorv32-f0b824ad9a0d9c4a010baf62114009c847f6a94d.zip | |
Minor README changes
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 9 |
1 files changed, 3 insertions, 6 deletions
@@ -216,12 +216,9 @@ Example assembler code using the `custom0` mnemonic: #### maskirq -The "IRQ Mask" register contains a birtmask of masked (disabled) interrupts. -This opcodes writes a new value to the irq mask register and reads the old -value. - -Enable/disable interrupt sources. This instruction is encoded under the -`custom0` opcode: +The "IRQ Mask" register contains a bitmask of masked (disabled) interrupts. +This instruction writes a new value to the irq mask register and reads the old +value. This instruction is encoded under the `custom0` opcode: 0000011 00000 XXXXX 000 XXXXX 0001011 f7 rs2 rs f3 rd opcode |