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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-06 10:46:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-06 10:46:52 +0200 |
| commit | f4bb91b060211884fc0b85479fb6becf20daeb1f (patch) | |
| tree | d971e626fe57262b7830211644f043477b33c562 /firmware/irq.c | |
| parent | 490a7345191f9841fa953d18b27c8485171406ce (diff) | |
| download | picorv32-f4bb91b060211884fc0b85479fb6becf20daeb1f.tar.gz picorv32-f4bb91b060211884fc0b85479fb6becf20daeb1f.zip | |
RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"
Diffstat (limited to 'firmware/irq.c')
| -rw-r--r-- | firmware/irq.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/irq.c b/firmware/irq.c index aaa141d..13dcb57 100644 --- a/firmware/irq.c +++ b/firmware/irq.c @@ -30,7 +30,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs) else print_hex(instr, 4); print_str("\n"); - __asm__ volatile ("sbreak"); + __asm__ volatile ("ebreak"); } } @@ -62,7 +62,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs) if ((irqs & 2) != 0) { if (instr == 0x00100073 || instr == 0x9002) { - print_str("SBREAK instruction at 0x"); + print_str("EBREAK instruction at 0x"); print_hex(pc, 8); print_str("\n"); } else { @@ -132,7 +132,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs) print_dec(timer_irq_count); print_str("\n"); - __asm__ volatile ("sbreak"); + __asm__ volatile ("ebreak"); } return regs; |