Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMER

1 files changed, 96 insertions, 0 deletions

diff --git a/firmware/start.S b/firmware/start.S
index c5e1901..9e9ad75 100644
--- a/firmware/start.S
+++ b/firmware/start.S
@@ -5,11 +5,16 @@
 // binary, for any purpose, commercial or non-commercial, and by any
 // means.
 
+#define ENABLE_QREGS
 #define ENABLE_RVTST
 #define ENABLE_SIEVE
 #define ENABLE_MULTST
 #define ENABLE_STATS
 
+#ifndef ENABLE_QREGS
+#  undef ENABLE_RVTST
+#endif
+
 #include "custom_ops.S"
 
 	.section .text
@@ -36,6 +41,8 @@ reset_vec:
 irq_vec:
 	/* save registers */
 
+#ifdef ENABLE_QREGS
+
 	setq q2, x1
 	setq q3, x2
 
@@ -81,6 +88,43 @@ irq_vec:
 	sw x30, 30*4(x1)
 	sw x31, 31*4(x1)
 
+#else // ENABLE_QREGS
+
+	sw gp,   0*4+0x200(zero)
+	sw x1,   1*4+0x200(zero)
+	sw x2,   2*4+0x200(zero)
+	sw x3,   3*4+0x200(zero)
+	sw x4,   4*4+0x200(zero)
+	sw x5,   5*4+0x200(zero)
+	sw x6,   6*4+0x200(zero)
+	sw x7,   7*4+0x200(zero)
+	sw x8,   8*4+0x200(zero)
+	sw x9,   9*4+0x200(zero)
+	sw x10, 10*4+0x200(zero)
+	sw x11, 11*4+0x200(zero)
+	sw x12, 12*4+0x200(zero)
+	sw x13, 13*4+0x200(zero)
+	sw x14, 14*4+0x200(zero)
+	sw x15, 15*4+0x200(zero)
+	sw x16, 16*4+0x200(zero)
+	sw x17, 17*4+0x200(zero)
+	sw x18, 18*4+0x200(zero)
+	sw x19, 19*4+0x200(zero)
+	sw x20, 20*4+0x200(zero)
+	sw x21, 21*4+0x200(zero)
+	sw x22, 22*4+0x200(zero)
+	sw x23, 23*4+0x200(zero)
+	sw x24, 24*4+0x200(zero)
+	sw x25, 25*4+0x200(zero)
+	sw x26, 26*4+0x200(zero)
+	sw x27, 27*4+0x200(zero)
+	sw x28, 28*4+0x200(zero)
+	sw x29, 29*4+0x200(zero)
+	sw x30, 30*4+0x200(zero)
+	sw x31, 31*4+0x200(zero)
+
+#endif // ENABLE_QREGS
+
 	/* call interrupt handler C function */
 
 	lui sp, %hi(irq_stack)
@@ -91,13 +135,19 @@ irq_vec:
 	addi a0, a0, %lo(irq_regs)
 
 	// arg1 = interrupt type
+#ifdef ENABLE_QREGS
 	getq a1, q1
+#else
+	addi a1, tp, 0
+#endif
 
 	// call to C function
 	jal ra, irq
 
 	/* restore registers */
 
+#ifdef ENABLE_QREGS
+
 	// new irq_regs address returned from C code in a0
 	addi x1, a0, 0
 
@@ -143,8 +193,54 @@ irq_vec:
 	getq x1, q1
 	getq x2, q2
 
+#else // ENABLE_QREGS
+
+	// new irq_regs address returned from C code in a0
+	addi a1, zero, 0x200
+	beq a0, a1, 1f
+	sbreak
+1:
+
+	lw gp,   0*4+0x200(zero)
+	lw x1,   1*4+0x200(zero)
+	lw x2,   2*4+0x200(zero)
+	// do not restore x3 (gp)
+	lw x4,   4*4+0x200(zero)
+	lw x5,   5*4+0x200(zero)
+	lw x6,   6*4+0x200(zero)
+	lw x7,   7*4+0x200(zero)
+	lw x8,   8*4+0x200(zero)
+	lw x9,   9*4+0x200(zero)
+	lw x10, 10*4+0x200(zero)
+	lw x11, 11*4+0x200(zero)
+	lw x12, 12*4+0x200(zero)
+	lw x13, 13*4+0x200(zero)
+	lw x14, 14*4+0x200(zero)
+	lw x15, 15*4+0x200(zero)
+	lw x16, 16*4+0x200(zero)
+	lw x17, 17*4+0x200(zero)
+	lw x18, 18*4+0x200(zero)
+	lw x19, 19*4+0x200(zero)
+	lw x20, 20*4+0x200(zero)
+	lw x21, 21*4+0x200(zero)
+	lw x22, 22*4+0x200(zero)
+	lw x23, 23*4+0x200(zero)
+	lw x24, 24*4+0x200(zero)
+	lw x25, 25*4+0x200(zero)
+	lw x26, 26*4+0x200(zero)
+	lw x27, 27*4+0x200(zero)
+	lw x28, 28*4+0x200(zero)
+	lw x29, 29*4+0x200(zero)
+	lw x30, 30*4+0x200(zero)
+	lw x31, 31*4+0x200(zero)
+
+#endif // ENABLE_QREGS
+
 	retirq
 
+#ifndef ENABLE_QREGS
+.balign 0x200
+#endif
 irq_regs:
 	// registers are saved to this memory region during interrupt handling
 	// the program counter is saved as register 0