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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-20 20:17:27 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-20 20:17:27 +0200 |
| commit | 51436b1c5017012fb1d666d8a7ffcb96b0906d73 (patch) | |
| tree | b31b03127316677e013ece1c53334ac1079319f7 /picosoc/README.md | |
| parent | 7639e6ebac26fafbff2c3e2a72e83cf5cd0c3a3e (diff) | |
| download | picorv32-51436b1c5017012fb1d666d8a7ffcb96b0906d73.tar.gz picorv32-51436b1c5017012fb1d666d8a7ffcb96b0906d73.zip | |
PicoSoC QSPI DDR progress
Diffstat (limited to 'picosoc/README.md')
| -rw-r--r-- | picosoc/README.md | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index 5a6413c..c112835 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -55,7 +55,7 @@ GPIO pins mapped to the 32 bit word at address 0x03000000. | 30:23 | Reserved (read 0) | | 22 | DDR Enable bit (reset=0) | | 21 | QSPI Enable bit (reset=0) | -| 20 | Continous Read Enable bit (reset=0) | +| 20 | XIP Enable bit (reset=0) | | 19:16 | Number of QSPI dummy cycles (reset=0) | | 15:12 | Reserved (read 0) | | 11:8 | IO Output enable bits in bit bang mode | @@ -64,3 +64,13 @@ GPIO pins mapped to the 32 bit word at address 0x03000000. | 4 | Serial clock line in bit bang mode | | 3:0 | IO data bits in bit bang mode | +The following settings for XIP/DDR/QSPI modes are valid: + +| XIP | DDR | QSPI | Read Command Byte | Mode Byte | +| :-: | :-: | :--: | :-------------------- | :-------: | +| 0 | 0 | 0 | 03h Read | N/A | +| 0 | 0 | 1 | EBh Quad I/O Read | FFh | +| 1 | 0 | 1 | EBh Quad I/O Read | A5h / FFh | +| 0 | 1 | 1 | EDh DDR Quad I/O Read | FFh | +| 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h / FFh | + |