diff options
| author | Clifford Wolf <clifford@clifford.at> | 2017-08-11 15:57:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-11 15:57:42 +0200 |
| commit | 78f2f5efd27765820849df4cfca2b9adc7bcb9b5 (patch) | |
| tree | 15a3da231698b09f2c7a15b26d3f81a0289f6925 /picosoc/README.md | |
| parent | 53b175d0fb036e114ce28c38831d7756afb834f5 (diff) | |
| download | picorv32-78f2f5efd27765820849df4cfca2b9adc7bcb9b5.tar.gz picorv32-78f2f5efd27765820849df4cfca2b9adc7bcb9b5.zip | |
Add support for QSPI DDR mode, Add SPI MEMIO config reg
Diffstat (limited to 'picosoc/README.md')
| -rw-r--r-- | picosoc/README.md | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index e70f87c..5d7e2d3 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -27,3 +27,32 @@ and upload them to a connected iCE40-HX8K Breakout Board. | [hx8kdemo.v](hx8kdemo.v) | FPGA-based example implementation on iCE40-HX8K Breakout Board | | [hx8kdemo.pcf](hx8kdemo.pcf) | Pin constraints for implementation on iCE40-HX8K Breakout Board | +### Memory map: + +| Address Range | Description | +| ------------------------ | --------------------------------------- | +| 0x00000000 .. 0x00FFFFFF | Internal SRAM | +| 0x01000000 .. 0x01FFFFFF | External Serial Flash | +| 0x02000000 .. 0x02000003 | SPI Flash Controller Config Register | +| 0x03000000 .. 0x00FFFFFF | Memory mapped user peripherals | + +The example design (hx8kdemo.v) and generic test bench (testbench.v) have 32 +GPIO pins mapped to the 32 bit word at address 0x03000000. + +### SPI Flash Controller Config Register: + +| Bit(s) | Description | +| -----: | --------------------------------------------------------- | +| 31 | MEMIO Enable (reset=1, set to 0 to bit bang SPI commands) | +| 30:20 | Reserved (read 0) | +| 19:16 | IO Output enable bits in bit bang mode | +| 15:14 | Reserved (read 0) | +| 13 | Chip select (CS) line in bit bang mode | +| 12 | Serial clock line in bit bang mode | +| 11:8 | IO data bits in bit bang mode | +| 7 | Reserved (read 0) | +| 6 | DDR Enable bit (reset=0) | +| 5 | QSPI Enable bit (reset=0) | +| 4 | Continous Read Enable bit (reset=0) | +| 3:0 | Number of QSPI dummy cycles (reset=0) | + |