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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-21 15:50:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-21 15:50:50 +0200 |
| commit | c06ba38113b98b4996aed6d523667444a5d83bf6 (patch) | |
| tree | 4907c5954f6b9da665a07574c2ac512f8360f689 /picosoc/README.md | |
| parent | c00811e8e45d535f6a260b2e78fa7f68df3d91f5 (diff) | |
| download | picorv32-c06ba38113b98b4996aed6d523667444a5d83bf6.tar.gz picorv32-c06ba38113b98b4996aed6d523667444a5d83bf6.zip | |
Add PicoSoC spimem Dual I/O support
Diffstat (limited to 'picosoc/README.md')
| -rw-r--r-- | picosoc/README.md | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index c112835..aec6142 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -55,8 +55,8 @@ GPIO pins mapped to the 32 bit word at address 0x03000000. | 30:23 | Reserved (read 0) | | 22 | DDR Enable bit (reset=0) | | 21 | QSPI Enable bit (reset=0) | -| 20 | XIP Enable bit (reset=0) | -| 19:16 | Number of QSPI dummy cycles (reset=0) | +| 20 | CRM Enable bit (reset=0) | +| 19:16 | Read latency (dummy) cycles (reset=0) | | 15:12 | Reserved (read 0) | | 11:8 | IO Output enable bits in bit bang mode | | 7:6 | Reserved (read 0) | @@ -64,13 +64,15 @@ GPIO pins mapped to the 32 bit word at address 0x03000000. | 4 | Serial clock line in bit bang mode | | 3:0 | IO data bits in bit bang mode | -The following settings for XIP/DDR/QSPI modes are valid: - -| XIP | DDR | QSPI | Read Command Byte | Mode Byte | -| :-: | :-: | :--: | :-------------------- | :-------: | -| 0 | 0 | 0 | 03h Read | N/A | -| 0 | 0 | 1 | EBh Quad I/O Read | FFh | -| 1 | 0 | 1 | EBh Quad I/O Read | A5h / FFh | -| 0 | 1 | 1 | EDh DDR Quad I/O Read | FFh | -| 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h / FFh | +The following settings for CRM/DDR/QSPI modes are valid: + +| CRM | QSPI | DDR | Read Command Byte | Mode Byte | +| :-: | :--: | :-: | :-------------------- | :-------: | +| 0 | 0 | 0 | 03h Read | N/A | +| 0 | 0 | 1 | BBh Dual I/O Read | FFh | +| 1 | 0 | 1 | BBh Dual I/O Read | A5h | +| 0 | 1 | 0 | EBh Quad I/O Read | FFh | +| 1 | 1 | 0 | EBh Quad I/O Read | A5h | +| 0 | 1 | 1 | EDh DDR Quad I/O Read | FFh | +| 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h | |