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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-16 22:08:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-16 22:08:05 +0200 |
| commit | dabebeb0084a541fb16690f600ad153edbc1cbe9 (patch) | |
| tree | 73acf14a47d5ee41f5b2582b0a9289af723fee0c /picosoc/README.md | |
| parent | 76124b8649c85e4e7218b776733d93d364e28845 (diff) | |
| download | picorv32-dabebeb0084a541fb16690f600ad153edbc1cbe9.tar.gz picorv32-dabebeb0084a541fb16690f600ad153edbc1cbe9.zip | |
Improve PicoSoC demo firmware (read flash ID is working now)
Diffstat (limited to 'picosoc/README.md')
| -rw-r--r-- | picosoc/README.md | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index 2fd558c..b3db5e7 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -38,8 +38,8 @@ and upload them to a connected iCE40-HX8K Breakout Board. | 0x02000008 .. 0x0200000B | UART Send/Recv Data Register | | 0x03000000 .. 0xFFFFFFFF | Memory mapped user peripherals | -The addresses in the internal SRAM region beyond the end of the physical -SRAM map to the corresponding addresses in serial flash. +Reading from the addresses in the internal SRAM region beyond the end of the +physical SRAM will read from the corresponding addresses in serial flash. Reading from the UART Send/Recv Data Register will return the last received byte, or -1 (all 32 bits set) when the receive buffer is empty. @@ -52,15 +52,15 @@ GPIO pins mapped to the 32 bit word at address 0x03000000. | Bit(s) | Description | | -----: | --------------------------------------------------------- | | 31 | MEMIO Enable (reset=1, set to 0 to bit bang SPI commands) | -| 30:20 | Reserved (read 0) | -| 19:16 | IO Output enable bits in bit bang mode | -| 15:14 | Reserved (read 0) | -| 13 | Chip select (CS) line in bit bang mode | -| 12 | Serial clock line in bit bang mode | -| 11:8 | IO data bits in bit bang mode | -| 7 | Reserved (read 0) | -| 6 | DDR Enable bit (reset=0) | -| 5 | QSPI Enable bit (reset=0) | -| 4 | Continous Read Enable bit (reset=0) | -| 3:0 | Number of QSPI dummy cycles (reset=0) | +| 30:23 | Reserved (read 0) | +| 22 | DDR Enable bit (reset=0) | +| 21 | QSPI Enable bit (reset=0) | +| 20 | Continous Read Enable bit (reset=0) | +| 19:16 | Number of QSPI dummy cycles (reset=0) | +| 15:12 | Reserved (read 0) | +| 11:8 | IO Output enable bits in bit bang mode | +| 7:6 | Reserved (read 0) | +| 5 | Chip select (CS) line in bit bang mode | +| 4 | Serial clock line in bit bang mode | +| 3:0 | IO data bits in bit bang mode | |