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| author | Clifford Wolf <clifford@clifford.at> | 2017-08-07 15:13:27 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-07 15:13:27 +0200 |
| commit | db2222ec02a926a26a450d11382e9f7414a519f6 (patch) | |
| tree | 9ceb3f0bd52963825a16e77da54259a1ed05b56e /picosoc/README.md | |
| parent | caef4e3753d2c76de5d7030fcc2e3a1c331c64c6 (diff) | |
| download | picorv32-db2222ec02a926a26a450d11382e9f7414a519f6.tar.gz picorv32-db2222ec02a926a26a450d11382e9f7414a519f6.zip | |
Refactor picosoc code
Diffstat (limited to 'picosoc/README.md')
| -rw-r--r-- | picosoc/README.md | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index bf3bff6..e70f87c 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -5,23 +5,25 @@ PicoSoC - A simple example SoC using PicoRV32 This is a simple PicoRV32 example design that can run code directly from an SPI flash chip. This example design uses the Lattice iCE40-HX8K Breakout Board. -The flash is mapped to the memory region starting at 0x80000000. The reset -vector is set to 0x80100000, i.e. at the 1MB offset inside the flash memory. +The flash is mapped to the memory region starting at 0x01000000. The reset +vector is set to 0x01100000, i.e. at the 1MB offset inside the flash memory. A small scratchpad memory (default 256 words, i.e. 1 kB) is mapped to address -0x00000000. A simple GPIO controller is mapped to address 0xC0000000. +0x00000000. Run `make test` to run the test bench (and create `testbench.vcd`). Run `make prog` to build the configuration bit-stream and firmware images and upload them to a connected iCE40-HX8K Breakout Board. -| File | Description | -| --------------------------- | --------------------------------------------------------------- | -| [picosoc.v](picosoc.v) | Top-level Verilog module for the design | -| [spimemio.v](spimemio.v) | Memory controller that interfaces to external SPI flash | -| [spiflash.v](spiflash.v) | Simulation model of an SPI flash (used by testbench.v) | -| [testbench.v](testbench.v) | Simple test bench for the design (requires firmware.hex). | -| [firmware.s](firmware.s) | Assembler source for firmware.hex/firmware.bin. | -| [pinout.pcf](pinout.pcf) | Pin constraints for implementation on iCE40-HX8K Breakout Board | +| File | Description | +| ----------------------------- | --------------------------------------------------------------- | +| [picosoc.v](picosoc.v) | Top-level PicoSoC Verilog module | +| [picosoc.v](picosoc.v) | Top-level PicoSoC Verilog module | +| [spimemio.v](spimemio.v) | Memory controller that interfaces to external SPI flash | +| [spiflash.v](spiflash.v) | Simulation model of an SPI flash (used by testbench.v) | +| [testbench.v](testbench.v) | Simple test bench for the design (requires firmware.hex). | +| [firmware.s](firmware.s) | Assembler source for firmware.hex/firmware.bin. | +| [hx8kdemo.v](hx8kdemo.v) | FPGA-based example implementation on iCE40-HX8K Breakout Board | +| [hx8kdemo.pcf](hx8kdemo.pcf) | Pin constraints for implementation on iCE40-HX8K Breakout Board | |