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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-21 18:53:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-09-21 18:53:54 +0200 |
| commit | ebc4d1c4a17b396d48df234c7f8fa3a417ec98c7 (patch) | |
| tree | df5f02c82b0f507ff44f237dfbf74e715782b109 /picosoc/README.md | |
| parent | 45bd9b81ea43668e710489751cb57ceb86ed7d69 (diff) | |
| download | picorv32-ebc4d1c4a17b396d48df234c7f8fa3a417ec98c7.tar.gz picorv32-ebc4d1c4a17b396d48df234c7f8fa3a417ec98c7.zip | |
Update README.md
Diffstat (limited to 'picosoc/README.md')
| -rw-r--r-- | picosoc/README.md | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index aec6142..7638dbc 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -76,3 +76,14 @@ The following settings for CRM/DDR/QSPI modes are valid: | 0 | 1 | 1 | EDh DDR Quad I/O Read | FFh | | 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h | +The following plot visualizes the relative performance of the different configurations: + + + +Consult the datasheet for your SPI flash to learn which configurations are supported +by the chip and what the maximum clock frequencies are for each configuration. + +For Quad I/O mode the QUAD flag in CR1V must be set before enabling Quad I/O in the +SPI master. Either set it by writing the corresponding bit in CR1NV once, or by writing +it from your device firmware at every bootup. (See `set_flash_qspi_flag()` in +`firmware.c` for an example for the latter.) |