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authorClifford Wolf <clifford@clifford.at>2018-08-19 13:38:59 +0200
committerClifford Wolf <clifford@clifford.at>2018-08-19 13:38:59 +0200
commit68c69136b969773e122e2c7ac92e42feca74a828 (patch)
treee7c6bf7cf0c5f59d2704cf2a700d2e72200f7f53 /picosoc/firmware.c
parent1afe3af452212b424a96d2e0d1b89aab0259e50e (diff)
downloadpicorv32-68c69136b969773e122e2c7ac92e42feca74a828.tar.gz
picorv32-68c69136b969773e122e2c7ac92e42feca74a828.zip
Add icebreaker example PicoSoC implementation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'picosoc/firmware.c')
-rw-r--r--picosoc/firmware.c118
1 files changed, 102 insertions, 16 deletions
diff --git a/picosoc/firmware.c b/picosoc/firmware.c
index 2db2588..be3bf52 100644
--- a/picosoc/firmware.c
+++ b/picosoc/firmware.c
@@ -1,6 +1,29 @@
+/*
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
#include <stdint.h>
#include <stdbool.h>
+#if !defined(ICEBREAKER) && !defined(HX8KDEMO)
+# error "Set -DICEBREAKER or -DHX8KDEMO when compiling firmware.c"
+#endif
+
// a pointer to this is a null pointer, but the compiler does not
// know that because "sram" is a linker symbol from sections.lds.
extern uint32_t sram;
@@ -28,11 +51,10 @@ void flashio(uint8_t *data, int len, uint8_t wrencmd)
((void(*)(uint8_t*, uint32_t, uint32_t))func)(data, len, wrencmd);
}
+#ifdef HX8KBOARD
void set_flash_qspi_flag()
{
uint8_t buffer[8];
-
-#if 1
uint32_t addr_cr1v = 0x800002;
// Read Any Register (RDAR 65h)
@@ -52,26 +74,26 @@ void set_flash_qspi_flag()
buffer[3] = addr_cr1v;
buffer[4] = cr1v | 2; // Enable QSPI
flashio(buffer, 5, 0x06);
-#else
- // Read Status Register 1 (RDSR1 05h)
- buffer[0] = 0x05;
- buffer[1] = 0x00; // rdata
- flashio(buffer, 2, 0);
- uint8_t sr1v = buffer[1];
+}
+#endif
+
+#ifdef ICEBREAKER
+void set_flash_qspi_flag()
+{
+ uint8_t buffer[8];
// Read Configuration Registers (RDCR1 35h)
buffer[0] = 0x35;
buffer[1] = 0x00; // rdata
flashio(buffer, 2, 0);
- uint8_t cr1v = buffer[1];
+ uint8_t sr2 = buffer[1];
- // Write Enable (WREN 06h) + Write Registers (WRR 01h)
- buffer[0] = 0x01;
- buffer[1] = sr1v;
- buffer[2] = cr1v | 2; // Enable QSPI
- flashio(buffer, 3, 0x06);
-#endif
+ // Write Enable Volatile (50h) + Write Status Register 2 (31h)
+ buffer[0] = 0x31;
+ buffer[1] = sr2 | 2; // Enable QSPI
+ flashio(buffer, 2, 0x50);
}
+#endif
void set_flash_latency(uint8_t value)
{
@@ -185,6 +207,7 @@ void cmd_read_flash_id()
// --------------------------------------------------------
+#ifdef HX8KDEMO
uint8_t cmd_read_flash_regs_print(uint32_t addr, const char *name)
{
set_flash_latency(8);
@@ -213,6 +236,70 @@ void cmd_read_flash_regs()
uint8_t cr3v = cmd_read_flash_regs_print(0x800004, "CR3V");
uint8_t vdlp = cmd_read_flash_regs_print(0x800005, "VDLP");
}
+#endif
+
+#ifdef ICEBREAKER
+uint8_t cmd_read_flash_reg(uint8_t cmd)
+{
+ set_flash_latency(8);
+
+ uint8_t buffer[2] = {cmd, 0};
+ flashio(buffer, 2, 0);
+ return buffer[1];
+}
+
+void print_reg_bit(int val, const char *name)
+{
+ for (int i = 0; i < 12; i++) {
+ if (*name == 0)
+ putchar(' ');
+ else
+ putchar(*(name++));
+ }
+
+ putchar(val ? '1' : '0');
+ putchar('\n');
+}
+
+void cmd_read_flash_regs()
+{
+ putchar('\n');
+
+ uint8_t sr1 = cmd_read_flash_reg(0x05);
+ uint8_t sr2 = cmd_read_flash_reg(0x35);
+ uint8_t sr3 = cmd_read_flash_reg(0x15);
+
+ print_reg_bit(sr1 & 0x01, "S0 (BUSY)");
+ print_reg_bit(sr1 & 0x02, "S1 (WEL)");
+ print_reg_bit(sr1 & 0x04, "S2 (BP0)");
+ print_reg_bit(sr1 & 0x08, "S3 (BP1)");
+ print_reg_bit(sr1 & 0x10, "S4 (BP2)");
+ print_reg_bit(sr1 & 0x20, "S5 (TB)");
+ print_reg_bit(sr1 & 0x40, "S6 (SEC)");
+ print_reg_bit(sr1 & 0x80, "S7 (SRP)");
+ putchar('\n');
+
+ print_reg_bit(sr2 & 0x01, "S8 (SRL)");
+ print_reg_bit(sr2 & 0x02, "S9 (QE)");
+ print_reg_bit(sr2 & 0x04, "S10 ----");
+ print_reg_bit(sr2 & 0x08, "S11 (LB1)");
+ print_reg_bit(sr2 & 0x10, "S12 (LB2)");
+ print_reg_bit(sr2 & 0x20, "S13 (LB3)");
+ print_reg_bit(sr2 & 0x40, "S14 (CMP)");
+ print_reg_bit(sr2 & 0x80, "S15 (SUS)");
+ putchar('\n');
+
+ print_reg_bit(sr3 & 0x01, "S16 ----");
+ print_reg_bit(sr3 & 0x02, "S17 ----");
+ print_reg_bit(sr3 & 0x04, "S18 (WPS)");
+ print_reg_bit(sr3 & 0x08, "S19 ----");
+ print_reg_bit(sr3 & 0x10, "S20 ----");
+ print_reg_bit(sr3 & 0x20, "S21 (DRV0)");
+ print_reg_bit(sr3 & 0x40, "S22 (DRV1)");
+ print_reg_bit(sr3 & 0x80, "S23 (HOLD)");
+ putchar('\n');
+}
+#endif
// --------------------------------------------------------
@@ -483,4 +570,3 @@ void main()
}
}
}
-