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authorClifford Wolf <clifford@clifford.at>2017-08-11 15:57:42 +0200
committerClifford Wolf <clifford@clifford.at>2017-08-11 15:57:42 +0200
commit78f2f5efd27765820849df4cfca2b9adc7bcb9b5 (patch)
tree15a3da231698b09f2c7a15b26d3f81a0289f6925 /picosoc/picosoc.v
parent53b175d0fb036e114ce28c38831d7756afb834f5 (diff)
downloadpicorv32-78f2f5efd27765820849df4cfca2b9adc7bcb9b5.tar.gz
picorv32-78f2f5efd27765820849df4cfca2b9adc7bcb9b5.zip
Add support for QSPI DDR mode, Add SPI MEMIO config reg
Diffstat (limited to 'picosoc/picosoc.v')
-rw-r--r--picosoc/picosoc.v14
1 files changed, 11 insertions, 3 deletions
diff --git a/picosoc/picosoc.v b/picosoc/picosoc.v
index 23260c9..da9b9a9 100644
--- a/picosoc/picosoc.v
+++ b/picosoc/picosoc.v
@@ -69,8 +69,12 @@ module picosoc (
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
- assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready;
- assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata : 32'h xxxx_xxxx;
+ wire spimemio_cfgreg_sel = (mem_addr == 32'h 0200_0000);
+ wire [31:0] spimemio_cfgreg_do;
+
+ assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel;
+ assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
+ spimemio_cfgreg_sel ? spimemio_cfgreg_do : 32'h xxxx_xxxx;
picorv32 #(
.STACKADDR(STACKADDR),
@@ -111,7 +115,11 @@ module picosoc (
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
- .flash_io3_di (flash_io3_di)
+ .flash_io3_di (flash_io3_di),
+
+ .cfgreg_we(spimemio_cfgreg_sel ? mem_wstrb : 4'b 0000),
+ .cfgreg_di(mem_wdata),
+ .cfgreg_do(spimemio_cfgreg_do)
);
reg [31:0] memory [0:MEM_WORDS-1];