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| author | Clifford Wolf <clifford@clifford.at> | 2017-08-07 16:27:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-07 16:27:57 +0200 |
| commit | ff7855900d4f4b8d3ccd840e54f5d9c940c4f7e4 (patch) | |
| tree | 68d252d18a336bb88504e9b636d26cacb30ad1b8 /picosoc/spiflash.v | |
| parent | db2222ec02a926a26a450d11382e9f7414a519f6 (diff) | |
| download | picorv32-ff7855900d4f4b8d3ccd840e54f5d9c940c4f7e4.tar.gz picorv32-ff7855900d4f4b8d3ccd840e54f5d9c940c4f7e4.zip | |
Refactor picosoc flash_io interfaces
Diffstat (limited to 'picosoc/spiflash.v')
| -rw-r--r-- | picosoc/spiflash.v | 33 |
1 files changed, 20 insertions, 13 deletions
diff --git a/picosoc/spiflash.v b/picosoc/spiflash.v index c1e9615..6e6137f 100644 --- a/picosoc/spiflash.v +++ b/picosoc/spiflash.v @@ -15,15 +15,23 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * - * Supported commands: - * AB, B9, FF, 03, EB, ED - * - * Well written SPI flash data sheets: - * Cypress S25FL064L http://www.cypress.com/file/316661/download - * */ +`timescale 1 ns / 1 ps + +// +// Simple SPI flash simulation model +// +// This model samples io input signals 1ns before the SPI clock edge and +// updates output signals 1ns after the SPI clock edge. +// +// Supported commands: +// AB, B9, FF, 03, EB, ED +// +// Well written SPI flash data sheets: +// Cypress S25FL064L http://www.cypress.com/file/316661/download +// + module spiflash ( input csb, input clk, @@ -47,7 +55,6 @@ module spiflash ( reg [7:0] spi_out; reg spi_io_vld; - reg qspi_active = 0; reg powered_up = 0; localparam [3:0] mode_spi = 1; @@ -69,10 +76,10 @@ module spiflash ( reg io2_dout = 0; reg io3_dout = 0; - assign io0 = io0_oe ? io0_dout : 1'bz; - assign io1 = io1_oe ? io1_dout : 1'bz; - assign io2 = io2_oe ? io2_dout : 1'bz; - assign io3 = io3_oe ? io3_dout : 1'bz; + assign #1 io0 = io0_oe ? io0_dout : 1'bz; + assign #1 io1 = io1_oe ? io1_dout : 1'bz; + assign #1 io2 = io2_oe ? io2_dout : 1'bz; + assign #1 io3 = io3_oe ? io3_dout : 1'bz; wire io0_delayed; wire io1_delayed; @@ -105,7 +112,7 @@ module spiflash ( powered_up = 0; if (spi_cmd == 8'h ff) - qspi_active = 0; + xip_cmd = 0; end if (powered_up && spi_cmd == 'h 03) begin |