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authorClifford Wolf <clifford@clifford.at>2017-09-19 15:32:41 +0200
committerClifford Wolf <clifford@clifford.at>2017-09-19 15:32:41 +0200
commit7639e6ebac26fafbff2c3e2a72e83cf5cd0c3a3e (patch)
treed344f2a29afb2d11890425ca52e87f5ad6812b88 /picosoc/start.s
parent2cc1256ce7aab8637d82d91506cdeb73d42604b2 (diff)
downloadpicorv32-7639e6ebac26fafbff2c3e2a72e83cf5cd0c3a3e.tar.gz
picorv32-7639e6ebac26fafbff2c3e2a72e83cf5cd0c3a3e.zip
PicoSoC QSPI and XIP now working (tested in hardware)
Diffstat (limited to 'picosoc/start.s')
-rw-r--r--picosoc/start.s19
1 files changed, 17 insertions, 2 deletions
diff --git a/picosoc/start.s b/picosoc/start.s
index 5b051b0..9a285d1 100644
--- a/picosoc/start.s
+++ b/picosoc/start.s
@@ -45,6 +45,7 @@ j loop
flashio_worker_begin:
# a0 ... data pointer
# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
# address of SPI ctrl reg
li t0, 0x02000000
@@ -54,8 +55,22 @@ li t1, 0x120
sh t1, 0(t0)
# Enable Manual SPI Ctrl
-li t1, 0x00
-sb t1, 3(t0)
+sb zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb t1, 0(t0)
# SPI transfer
flashio_worker_L1: