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authorOlof Kindgren <olof.kindgren@gmail.com>2018-05-12 22:11:30 +0200
committerOlof Kindgren <olof.kindgren@gmail.com>2018-07-27 23:23:41 +0200
commit12274e9f8ab4cf50a3fb3c3a3068b1651be7f091 (patch)
tree082674b19e1246d49fe28f41660b1f80ef33f50e /picosoc
parent80f128713d8183cd9b477754542d9bb321bc7f2b (diff)
downloadpicorv32-12274e9f8ab4cf50a3fb3c3a3068b1651be7f091.tar.gz
picorv32-12274e9f8ab4cf50a3fb3c3a3068b1651be7f091.zip
Add FuseSoC .core file for hx8kdemo
The core file specifies targets for FPGA implementation (fusesoc build hx8kdemo) and simulation (fusesoc run --tool=<tool> --target=sim hx8kdemo --firmware=path/to/firmware.he). Simulation has been tested successfully with icarus, modelsim and xsim
Diffstat (limited to 'picosoc')
-rw-r--r--picosoc/hx8kdemo.core35
1 files changed, 35 insertions, 0 deletions
diff --git a/picosoc/hx8kdemo.core b/picosoc/hx8kdemo.core
new file mode 100644
index 0000000..97a1989
--- /dev/null
+++ b/picosoc/hx8kdemo.core
@@ -0,0 +1,35 @@
+CAPI=2:
+
+name : ::hx8kdemo:0
+
+filesets:
+ hx8kdemo:
+ files: [hx8kdemo.v]
+ file_type : verilogSource
+ depend : [picosoc]
+ hx8ksim:
+ files:
+ - hx8kdemo_tb.v
+ file_type : verilogSource
+ depend : [spiflash, "yosys:techlibs:ice40"]
+
+ constraints:
+ files: [hx8kdemo.pcf]
+ file_type : PCF
+
+targets:
+ synth:
+ default_tool : icestorm
+ filesets : [constraints, hx8kdemo]
+ tools:
+ icestorm:
+ arachne_pnr_options : [-d, 8k]
+ toplevel : [hx8kdemo]
+ sim:
+ default_tool : icarus
+ filesets : [hx8kdemo, hx8ksim]
+ tools:
+ xsim:
+ xelab_options : [--timescale, 1ns/1ps]
+
+ toplevel : [testbench]