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authorOlof Kindgren <olof.kindgren@gmail.com>2018-05-11 23:27:53 +0200
committerOlof Kindgren <olof.kindgren@gmail.com>2018-07-26 23:26:43 +0200
commit262da6444cd653eae57adc400ccaf8cea330deda (patch)
treec5e04a3d1725246afad40a0029727b90240fab49 /picosoc
parent9b6ea045f9b539b0f708d71962716e5dde865181 (diff)
downloadpicorv32-262da6444cd653eae57adc400ccaf8cea330deda.tar.gz
picorv32-262da6444cd653eae57adc400ccaf8cea330deda.zip
Add FuseSoC .core file for SPI Flash model
This allows other cores to depend on spiflash. Can also be used to run the spiflash testbench with fusesoc run --tool=<tool> spiflash --firmware=path/to/firmware.hex This has been tested with icarus, modelsim and xsim. Fails with isim If --tool is left out, icarus will be used as default
Diffstat (limited to 'picosoc')
-rw-r--r--picosoc/spiflash.core24
1 files changed, 24 insertions, 0 deletions
diff --git a/picosoc/spiflash.core b/picosoc/spiflash.core
new file mode 100644
index 0000000..1b7d153
--- /dev/null
+++ b/picosoc/spiflash.core
@@ -0,0 +1,24 @@
+CAPI=2:
+
+name : ::spiflash:0
+
+filesets:
+ model:
+ files : [spiflash.v]
+ file_type : verilogSource
+ tb:
+ files : [spiflash_tb.v]
+ file_type : verilogSource
+
+targets:
+ default:
+ default_tool : icarus
+ filesets : [model, "is_toplevel? (tb)"]
+ parameters : [firmware]
+ toplevel : [testbench]
+
+parameters :
+ firmware:
+ datatype : file
+ description : Initial SPI Flash contents (in verilog hex format)
+ paramtype : plusarg