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author | Clifford Wolf <clifford@clifford.at> | 2017-10-01 15:45:46 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-10-01 15:45:46 +0200 |
commit | ad08edd2e54494e4894c4534cf5f125ac61ba46e (patch) | |
tree | 86f5d3e96ce9186b38ba7739419e600a0473babe /picosoc | |
parent | 500db14e445c7cd8fc3d80aed28a827c8b7a608c (diff) | |
download | picorv32-ad08edd2e54494e4894c4534cf5f125ac61ba46e.tar.gz picorv32-ad08edd2e54494e4894c4534cf5f125ac61ba46e.zip |
Add PICORV32_REGS mechanism for ASIC sram instantiation
Diffstat (limited to 'picosoc')
-rw-r--r-- | picosoc/.gitignore | 1 | ||||
-rw-r--r-- | picosoc/Makefile | 7 | ||||
-rw-r--r-- | picosoc/picosoc.v | 67 |
3 files changed, 63 insertions, 12 deletions
diff --git a/picosoc/.gitignore b/picosoc/.gitignore index c09322d..4a2e42e 100644 --- a/picosoc/.gitignore +++ b/picosoc/.gitignore @@ -12,3 +12,4 @@ /hx8kdemo_syn_tb.vvp /hx8kdemo_tb.vvp /testbench.vcd +/cmos.log diff --git a/picosoc/Makefile b/picosoc/Makefile index 835cc05..39e3982 100644 --- a/picosoc/Makefile +++ b/picosoc/Makefile @@ -52,11 +52,16 @@ spiflash_tb: spiflash_tb.vvp firmware.hex spiflash_tb.vvp: spiflash.v spiflash_tb.v iverilog -s testbench -o $@ $^ +# ---- ASIC Synthesis Tests ---- + +cmos.log: spimemio.v simpleuart.v picosoc.v ../picorv32.v + yosys -l cmos.log -p 'synth -top picosoc; abc -g cmos2; opt -fast; stat' $^ + # ---- Clean ---- clean: rm -f testbench.vvp testbench.vcd spiflash_tb.vvp spiflash_tb.vcd - rm -f firmware.elf firmware.hex firmware.bin + rm -f firmware.elf firmware.hex firmware.bin cmos.log rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp diff --git a/picosoc/picosoc.v b/picosoc/picosoc.v index 0402749..0f82df5 100644 --- a/picosoc/picosoc.v +++ b/picosoc/picosoc.v @@ -17,6 +17,12 @@ * */ +`ifdef PICORV32_V +`error "picosoc.v must be read before picorv32.v!" +`endif + +`define PICORV32_REGS picosoc_regs + module picosoc ( input clk, input resetn, @@ -82,7 +88,7 @@ module picosoc ( wire [31:0] spimem_rdata; reg ram_ready; - reg [31:0] ram_rdata; + wire [31:0] ram_rdata; assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); assign iomem_wstrb = mem_wstrb; @@ -178,17 +184,56 @@ module picosoc ( .reg_dat_wait(simpleuart_reg_dat_wait) ); - reg [31:0] memory [0:MEM_WORDS-1]; + always @(posedge clk) + ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS; + + picosoc_mem #(.WORDS(MEM_WORDS)) memory ( + .clk(clk), + .wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0), + .addr(mem_addr[23:2]), + .wdata(mem_wdata), + .rdata(ram_rdata) + ); +endmodule + +// Implementation note: +// Replace the following two modules with wrappers for your SRAM cells. + +module picosoc_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:31]; + + always @(posedge clk) + if (wen) regs[waddr[4:0]] <= wdata; + + assign rdata1 = regs[raddr1[4:0]]; + assign rdata2 = regs[raddr2[4:0]]; +endmodule + +module picosoc_mem #( + parameter integer WORDS = 256 +) ( + input clk, + input [3:0] wen, + input [21:0] addr, + input [31:0] wdata, + output reg [31:0] rdata +); + reg [31:0] mem [0:WORDS-1]; always @(posedge clk) begin - ram_ready <= 0; - if (mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) begin - ram_ready <= 1; - ram_rdata <= memory[mem_addr >> 2]; - if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; - if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; - if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; - if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; - end + rdata <= mem[addr]; + if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0]; + if (wen[1]) mem[addr][15: 8] <= wdata[15: 8]; + if (wen[2]) mem[addr][23:16] <= wdata[23:16]; + if (wen[3]) mem[addr][31:24] <= wdata[31:24]; end endmodule + |