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| author | Tom Verbeure <tom_verbeure@yahoo.com> | 2016-08-30 22:36:06 -0700 |
|---|---|---|
| committer | Tom Verbeure <tom_verbeure@yahoo.com> | 2016-08-30 22:36:06 -0700 |
| commit | 209456a6c88c9460625c7fa7903f9561ba2005ad (patch) | |
| tree | a4f80e723075b633265a67439934b179e8824dea /scripts/quartus/synth_area_regular.qsf | |
| parent | 36152a568873864e9c980b9c62d73969f3900238 (diff) | |
| download | picorv32-209456a6c88c9460625c7fa7903f9561ba2005ad.tar.gz picorv32-209456a6c88c9460625c7fa7903f9561ba2005ad.zip | |
synth_area_large and synth_area_regular
Diffstat (limited to 'scripts/quartus/synth_area_regular.qsf')
| -rw-r--r-- | scripts/quartus/synth_area_regular.qsf | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/scripts/quartus/synth_area_regular.qsf b/scripts/quartus/synth_area_regular.qsf new file mode 100644 index 0000000..8507413 --- /dev/null +++ b/scripts/quartus/synth_area_regular.qsf @@ -0,0 +1,6 @@ +set_global_assignment -name DEVICE ep4ce40f29c7 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name TOP_LEVEL_ENTITY top_regular +set_global_assignment -name VERILOG_FILE ../synth_area_top.v +set_global_assignment -name VERILOG_FILE ../../../picorv32.v +set_global_assignment -name SDC_FILE ../synth_area.sdc |