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author | Guy Hutchison <guy@dryv.io> | 2018-10-18 20:33:40 +0000 |
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committer | Guy Hutchison <guy@dryv.io> | 2018-10-18 20:33:40 +0000 |
commit | 73318eaeabccfd90db6343c6a14280a3585a9853 (patch) | |
tree | 578c94c31f9ebf38e812ef7e1a798df0924d4dbd /scripts/romload/testbench.v | |
parent | f47ac81c89a517a57fd3c0656cab7a4075334328 (diff) | |
download | picorv32-73318eaeabccfd90db6343c6a14280a3585a9853.tar.gz picorv32-73318eaeabccfd90db6343c6a14280a3585a9853.zip |
Removed multiplier/divider
Diffstat (limited to 'scripts/romload/testbench.v')
-rw-r--r-- | scripts/romload/testbench.v | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/scripts/romload/testbench.v b/scripts/romload/testbench.v index 1e852cc..8c79e9b 100644 --- a/scripts/romload/testbench.v +++ b/scripts/romload/testbench.v @@ -3,7 +3,7 @@ //`undef WRITE_VCD `undef MEM8BIT -`define ROM_SIZE 32'h0000_0000 +`define ROM_SIZE 32'h0001_00FF //`define ROM_SIZE 32'h0000_0000 module testbench; @@ -30,9 +30,7 @@ module testbench; picorv32 #( .COMPRESSED_ISA(1), - .PROGADDR_RESET(32'h100), - .ENABLE_MUL(1), - .ENABLE_DIV(1) + .PROGADDR_RESET(32'h100) ) uut ( .clk (clk ), .resetn (resetn ), @@ -54,11 +52,19 @@ module testbench; end `else reg [31:0] memory [0:MEM_SIZE/4-1]; +`define data_lma 32'hc430 +`define data 32'h20000 +`define edata 32'h209b0 integer x; initial begin + // clear memory for (x=0; x<MEM_SIZE/4; x=x+1) memory[x] = 0; + // load rom contents $readmemh("firmware32.hex", memory); + // copy .data section + for (x=0; x<(`edata - `data); x=x+4) + memory[(`data+x)/4] = memory[(`data_lma+x)/4]; end `endif |