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author | Clifford Wolf <clifford@clifford.at> | 2016-04-08 16:08:23 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-04-08 16:08:23 +0200 |
commit | 33c0aaf5ded02bf947411749eac188bda70e1f67 (patch) | |
tree | 9d4d304f6eb5eec8068e095136ca52267db87cea /scripts/torture/test.sh | |
parent | 548abd6cce79c987cb051dd9e73caebafc3bcf40 (diff) | |
download | picorv32-33c0aaf5ded02bf947411749eac188bda70e1f67.tar.gz picorv32-33c0aaf5ded02bf947411749eac188bda70e1f67.zip |
Single test support in scripts/torture/
Diffstat (limited to 'scripts/torture/test.sh')
-rw-r--r-- | scripts/torture/test.sh | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/scripts/torture/test.sh b/scripts/torture/test.sh new file mode 100644 index 0000000..3b3e5c2 --- /dev/null +++ b/scripts/torture/test.sh @@ -0,0 +1,28 @@ +#!/bin/bash + +set -ex + + +## Generate test case + +if ! test -f test.S; then + cd riscv-torture + ./sbt generator/run + cp output/test.S ../test.S + cd .. +fi + + +## Compile test case and create reference + +riscv32-unknown-elf-gcc -m32 -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S +LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > test.ref +riscv32-unknown-elf-objcopy -O binary test.elf test.bin +python3 ../../firmware/makehex.py test.bin 4096 > test.hex + + +## Run test + +iverilog -o test.vvp testbench.v ../../picorv32.v +vvp test.vvp +hex=test.hex +ref=test.ref + |