Run torture test with random PicoRV32 configs

5 files changed, 54 insertions, 11 deletions

diff --git a/scripts/torture/.gitignore b/scripts/torture/.gitignore
index 9cae116..b58f70b 100644
--- a/scripts/torture/.gitignore
+++ b/scripts/torture/.gitignore
@@ -2,6 +2,7 @@
 riscv-fesvr
 riscv-isa-sim
 riscv-torture
+config.vh
 obj_dir
 tests
 test.S
diff --git a/scripts/torture/Makefile b/scripts/torture/Makefile
index 250dc6f..3a063c7 100644
--- a/scripts/torture/Makefile
+++ b/scripts/torture/Makefile
@@ -34,7 +34,10 @@ batch_list = $(shell bash -c 'for i in {0..999}; do printf "%03d\n" $$i; done')
 
 batch: $(addprefix tests/test_,$(addsuffix .ok,$(batch_list)))
 
-obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v
+config.vh: config.py riscv-torture/build.ok
+	python3 config.py
+
+obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v config.vh
 	verilator --exe -Wno-fatal --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
 	$(MAKE) -C obj_dir -f Vtestbench.mk
 
@@ -42,10 +45,10 @@ tests/testbench.vvp: testbench.v ../../picorv32.v
 	mkdir -p tests
 	iverilog -o tests/testbench.vvp testbench.v ../../picorv32.v
 
-tests/generated.ok: riscv-torture/build.ok
+tests/generated.ok: config.vh riscv-torture/build.ok
 	mkdir -p tests
 	rm -f riscv-torture/output/test_*
-	cd riscv-torture && ./sbt 'generator/run -n 1000'
+	cd riscv-torture && ./sbt 'generator/run -C config/test.config -n 1000'
 	touch tests/generated.ok
 
 define test_template
@@ -54,7 +57,8 @@ tests/test_$(1).S: tests/generated.ok
 	touch tests/test_$(1).S
 
 tests/test_$(1).elf: tests/test_$(1).S
-	riscv32-unknown-elf-gcc -m32 -march=RV32IMC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -I. -o tests/test_$(1).elf tests/test_$(1).S
+	riscv32-unknown-elf-gcc -m32 `sed '/march=/ ! d; s,^// ,-,;' config.vh` -ffreestanding -nostdlib \
+			-Wl,-Bstatic,-T,sections.lds -I. -o tests/test_$(1).elf tests/test_$(1).S
 
 tests/test_$(1).bin: tests/test_$(1).elf
 	riscv32-unknown-elf-objcopy -O binary tests/test_$(1).elf tests/test_$(1).bin
@@ -76,13 +80,14 @@ $(foreach id,$(batch_list),$(eval $(call test_template,$(id))))
 loop:
 	date +"%s %Y-%m-%d %H:%M:%S START" >> .looplog
 	+set -ex; while true; do \
-	  rm -rf tests; $(MAKE) batch; \
+	  rm -rf tests obj_dir config.vh; $(MAKE) batch; \
 	  date +"%s %Y-%m-%d %H:%M:%S NEXT" >> .looplog; \
 	done
 
 clean:
 	rm -rf tests obj_dir
-	rm -f test.S test.elf test.bin test.hex test.ref test.vvp test.vcd
+	rm -f config.vh test.S test.elf test.bin
+	rm -f test.hex test.ref test.vvp test.vcd
 
 mrproper: clean
 	rm -rf riscv-torture riscv-fesvr riscv-isa-sim
diff --git a/scripts/torture/config.py b/scripts/torture/config.py
new file mode 100644
index 0000000..478f046
--- /dev/null
+++ b/scripts/torture/config.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+
+import numpy as np
+
+compressed_isa = np.random.randint(2)
+enable_mul = np.random.randint(2)
+enable_div = np.random.randint(2)
+
+with open("config.vh", "w") as f:
+    print("// march=RV32I%s%s" % (
+            "M" if enable_mul or enable_div else "",
+            "C" if compressed_isa else ""), file=f)
+    print(".ENABLE_COUNTERS(%d)," % np.random.randint(2), file=f)
+    print(".ENABLE_COUNTERS64(%d)," % np.random.randint(2), file=f)
+    print(".ENABLE_REGS_DUALPORT(%d)," % np.random.randint(2), file=f)
+    print(".TWO_STAGE_SHIFT(%d)," % np.random.randint(2), file=f)
+    print(".BARREL_SHIFTER(%d)," % np.random.randint(2), file=f)
+    print(".TWO_CYCLE_COMPARE(%d)," % np.random.randint(2), file=f)
+    print(".TWO_CYCLE_ALU(%d)," % np.random.randint(2), file=f)
+    print(".CATCH_MISALIGN(%d)," % np.random.randint(2), file=f)
+    print(".CATCH_ILLINSN(%d)," % np.random.randint(2), file=f)
+    print(".COMPRESSED_ISA(%d)," % compressed_isa, file=f)
+    print(".ENABLE_MUL(%d)," % enable_mul, file=f)
+    print(".ENABLE_DIV(%d)" % enable_div, file=f)
+
+with open("riscv-torture/config/default.config", "r") as fi:
+    with open("riscv-torture/config/test.config", "w") as fo:
+        for line in fi:
+            line = line.strip()
+            if line.startswith("torture.generator.mul "):
+                line = "torture.generator.mul       %s" % ("true" if enable_mul else "false")
+            if line.startswith("torture.generator.divider "):
+                line = "torture.generator.divider   %s" % ("true" if enable_div else "false")
+            print(line, file=fo)
+
diff --git a/scripts/torture/test.sh b/scripts/torture/test.sh
index 5e431c7..eae1b75 100644
--- a/scripts/torture/test.sh
+++ b/scripts/torture/test.sh
@@ -5,9 +5,13 @@ set -ex
 
 ## Generate test case
 
+if ! test -f config.vh; then
+	python3 config.py
+fi
+
 if ! test -f test.S; then
 	cd riscv-torture
-	./sbt generator/run
+	./sbt "generator/run -C config/test.config"
 	cp output/test.S ../test.S
 	cd ..
 fi
@@ -15,7 +19,7 @@ fi
 
 ## Compile test case and create reference
 
-riscv32-unknown-elf-gcc -m32 -march=RV32IMC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
+riscv32-unknown-elf-gcc -m32 `sed '/march=/ ! d; s,^// ,-,;' config.vh` -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
 LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > test.ref
 riscv32-unknown-elf-objcopy -O binary test.elf test.bin
 python3 ../../firmware/makehex.py test.bin 4096 > test.hex
diff --git a/scripts/torture/testbench.v b/scripts/torture/testbench.v
index e0a6390..326de0e 100644
--- a/scripts/torture/testbench.v
+++ b/scripts/torture/testbench.v
@@ -38,9 +38,7 @@ module testbench (
 	end
 
 	picorv32 #(
-		.COMPRESSED_ISA(1),
-		.ENABLE_MUL(1),
-		.ENABLE_DIV(1)
+`include "config.vh"
 	) uut (
 		.clk         (clk         ),
 		.resetn      (resetn      ),