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author | Clifford Wolf <clifford@clifford.at> | 2015-07-09 02:48:14 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-07-09 02:48:14 +0200 |
commit | 94edf3565dcd4d3cb581216d9a035d047e50c0f6 (patch) | |
tree | cce04eb898739fb1558df05a8c8ac4ef03aefdc3 /scripts/vivado/system.v | |
parent | 2a04d0e52e3d36da7e4a391587548264016b32dd (diff) | |
download | picorv32-94edf3565dcd4d3cb581216d9a035d047e50c0f6.tar.gz picorv32-94edf3565dcd4d3cb581216d9a035d047e50c0f6.zip |
Vivado "system" example
Diffstat (limited to 'scripts/vivado/system.v')
-rw-r--r-- | scripts/vivado/system.v | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/scripts/vivado/system.v b/scripts/vivado/system.v new file mode 100644 index 0000000..86449a0 --- /dev/null +++ b/scripts/vivado/system.v @@ -0,0 +1,65 @@ +`timescale 1 ns / 1 ps + +module system ( + input clk, + input resetn, + output trap, + output reg [7:0] out_byte, + output reg out_byte_en +); + // 4096 32bit words = 16kB memory + parameter MEM_SIZE = 4096; + + wire mem_valid; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + reg [31:0] mem_rdata; + + wire mem_la_read; + wire mem_la_write; + wire [31:0] mem_la_addr; + wire [31:0] mem_la_wdata; + wire [3:0] mem_la_wstrb; + + picorv32 uut ( + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ), + .mem_la_read (mem_la_read ), + .mem_la_write(mem_la_write), + .mem_la_addr (mem_la_addr ), + .mem_la_wdata(mem_la_wdata), + .mem_la_wstrb(mem_la_wstrb) + ); + + reg [31:0] memory [0:MEM_SIZE-1]; + initial $readmemh("firmware.hex", memory); + + assign mem_ready = 1; + + always @(posedge clk) begin + out_byte_en <= 0; + mem_rdata <= memory[mem_la_addr >> 2]; + if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin + if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0]; + if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8]; + if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16]; + if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24]; + end + else + if (mem_la_write && mem_la_addr == 32'h1000_0000) begin + out_byte_en <= 1; + out_byte <= mem_la_wdata; + end + end +endmodule |