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authorClifford Wolf <clifford@clifford.at>2015-09-12 14:02:23 +0200
committerClifford Wolf <clifford@clifford.at>2015-09-12 14:02:23 +0200
commit00844092ee97ea69fc9d2e410dc80d148c8291c4 (patch)
treee427ef89b14cf1ab67dcdb98ad973015b2b51810 /scripts/yosys
parent686289adc5ed421fa116e0a695cdc43c746c8539 (diff)
downloadpicorv32-00844092ee97ea69fc9d2e410dc80d148c8291c4.tar.gz
picorv32-00844092ee97ea69fc9d2e410dc80d148c8291c4.zip
Added scripts/yosys/synth_gates
Diffstat (limited to 'scripts/yosys')
-rw-r--r--scripts/yosys/synth_gates.lib32
-rw-r--r--scripts/yosys/synth_gates.v30
-rw-r--r--scripts/yosys/synth_gates.ys14
3 files changed, 76 insertions, 0 deletions
diff --git a/scripts/yosys/synth_gates.lib b/scripts/yosys/synth_gates.lib
new file mode 100644
index 0000000..917c81d
--- /dev/null
+++ b/scripts/yosys/synth_gates.lib
@@ -0,0 +1,32 @@
+library(gates) {
+ cell(NOT) {
+ area: 2; // 7404 hex inverter
+ pin(A) { direction: input; }
+ pin(Y) { direction: output;
+ function: "A'"; }
+ }
+ cell(NAND) {
+ area: 3; // 7400 quad 2-input NAND gate
+ pin(A) { direction: input; }
+ pin(B) { direction: input; }
+ pin(Y) { direction: output;
+ function: "(A*B)'"; }
+ }
+ cell(NOR) {
+ area: 3; // 7402 quad 2-input NOR gate
+ pin(A) { direction: input; }
+ pin(B) { direction: input; }
+ pin(Y) { direction: output;
+ function: "(A+B)'"; }
+ }
+ cell(DFF) {
+ area: 6; // 7474 dual D positive edge triggered flip-flop
+ ff(IQ, IQN) { clocked_on: C;
+ next_state: D; }
+ pin(C) { direction: input;
+ clock: true; }
+ pin(D) { direction: input; }
+ pin(Q) { direction: output;
+ function: "IQ"; }
+ }
+}
diff --git a/scripts/yosys/synth_gates.v b/scripts/yosys/synth_gates.v
new file mode 100644
index 0000000..8e2504e
--- /dev/null
+++ b/scripts/yosys/synth_gates.v
@@ -0,0 +1,30 @@
+module top (
+ input clk, resetn,
+
+ output mem_valid,
+ output mem_instr,
+ input mem_ready,
+
+ output [31:0] mem_addr,
+ output [31:0] mem_wdata,
+ output [ 3:0] mem_wstrb,
+ input [31:0] mem_rdata
+);
+ picorv32 #(
+ .ENABLE_COUNTERS(0),
+ .LATCHED_MEM_RDATA(1),
+ .TWO_STAGE_SHIFT(0),
+ .CATCH_MISALIGN(0),
+ .CATCH_ILLINSN(0)
+ ) picorv32 (
+ .clk (clk ),
+ .resetn (resetn ),
+ .mem_valid(mem_valid),
+ .mem_instr(mem_instr),
+ .mem_ready(mem_ready),
+ .mem_addr (mem_addr ),
+ .mem_wdata(mem_wdata),
+ .mem_wstrb(mem_wstrb),
+ .mem_rdata(mem_rdata)
+ );
+endmodule
diff --git a/scripts/yosys/synth_gates.ys b/scripts/yosys/synth_gates.ys
new file mode 100644
index 0000000..311d767
--- /dev/null
+++ b/scripts/yosys/synth_gates.ys
@@ -0,0 +1,14 @@
+read_verilog synth_gates.v
+read_verilog ../../picorv32.v
+
+hierarchy -top top
+proc; flatten
+
+synth
+
+dfflibmap -prepare -liberty synth_gates.lib
+abc -dff -liberty synth_gates.lib
+dfflibmap -liberty synth_gates.lib
+
+stat
+write_blif synth_gates.blif