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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-30 01:46:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-30 01:46:25 +0200 |
| commit | 997c5ce341ce4fcc209992a9b9096651e767eb2d (patch) | |
| tree | b8f3e8ad65486b98b9e0d5e771480d7bedf8e982 /scripts/yosys | |
| parent | 56b2b4971d4177190679646c153f9723d16735b8 (diff) | |
| download | picorv32-997c5ce341ce4fcc209992a9b9096651e767eb2d.tar.gz picorv32-997c5ce341ce4fcc209992a9b9096651e767eb2d.zip | |
Added "make test_synth"
Diffstat (limited to 'scripts/yosys')
| -rw-r--r-- | scripts/yosys/synth_sim.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys new file mode 100644 index 0000000..b64e7e1 --- /dev/null +++ b/scripts/yosys/synth_sim.ys @@ -0,0 +1,7 @@ +# yosys synthesis script for post-synthesis simulation (make test_synth) + +read_verilog picorv32.v +chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi +hierarchy -top picorv32_axi +synth +write_verilog synth.v |