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author | Clifford Wolf <clifford@clifford.at> | 2015-06-06 20:14:58 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-06-06 20:14:58 +0200 |
commit | 9df9d7ff905d1d6c49221607efc9a04f042ea003 (patch) | |
tree | 6fd540920847108e6a21b4edb61be7f78308060e /scripts | |
parent | abe046575321153c0bed10525fe8d12b92e776b1 (diff) | |
download | picorv32-9df9d7ff905d1d6c49221607efc9a04f042ea003.tar.gz picorv32-9df9d7ff905d1d6c49221607efc9a04f042ea003.zip |
Improved Xilinx example
Diffstat (limited to 'scripts')
-rw-r--r-- | scripts/.gitignore | 4 | ||||
-rw-r--r-- | scripts/synth_vivado.tcl | 18 | ||||
-rw-r--r-- | scripts/synth_vivado.xdc | 1 | ||||
-rw-r--r-- | scripts/synth_vivado_soc.v | 58 |
4 files changed, 81 insertions, 0 deletions
diff --git a/scripts/.gitignore b/scripts/.gitignore new file mode 100644 index 0000000..74c116e --- /dev/null +++ b/scripts/.gitignore @@ -0,0 +1,4 @@ +fsm_encoding.os +synth_vivado.log +synth_vivado_*.backup.log +synth_vivado_syn.v diff --git a/scripts/synth_vivado.tcl b/scripts/synth_vivado.tcl new file mode 100644 index 0000000..1685721 --- /dev/null +++ b/scripts/synth_vivado.tcl @@ -0,0 +1,18 @@ + +# vivado -nojournal -log synth_vivado.log -mode batch -source synth_vivado.tcl + +read_verilog synth_vivado_soc.v +read_verilog ../picorv32.v +read_xdc synth_vivado.xdc + +synth_design -part xc7a15t-csg324 -top picorv32_axi +# synth_design -part xc7a15t-csg324 -top test_soc +opt_design +place_design +route_design + +report_utilization +report_timing + +write_verilog -force synth_vivado_syn.v + diff --git a/scripts/synth_vivado.xdc b/scripts/synth_vivado.xdc new file mode 100644 index 0000000..f2c7ea2 --- /dev/null +++ b/scripts/synth_vivado.xdc @@ -0,0 +1 @@ +create_clock -period 4.00 [get_ports clk] diff --git a/scripts/synth_vivado_soc.v b/scripts/synth_vivado_soc.v new file mode 100644 index 0000000..64d70ae --- /dev/null +++ b/scripts/synth_vivado_soc.v @@ -0,0 +1,58 @@ +`timescale 1 ns / 1 ps + +module test_soc ( + input clk, + input resetn, + output trap, + output [7:0] out_byte, + output out_byte_en, + + output monitor_valid, + output [31:0] monitor_addr, + output [31:0] monitor_data +); + parameter MEM_SIZE = 64*1024/4; + + wire mem_valid; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + wire [31:0] mem_rdata; + + picorv32 uut ( + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid(mem_valid), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_rdata(mem_rdata) + ); + + assign monitor_valid = mem_valid; + assign monitor_addr = mem_addr; + assign monitor_data = mem_wstrb ? mem_wdata : mem_rdata; + + reg [31:0] memory [0:MEM_SIZE-1]; + initial $readmemh("../firmware/firmware.hex", memory); + + assign mem_ready = 1; + assign mem_rdata = memory[mem_addr >> 2]; + + assign out_byte = mem_wdata[7:0]; + assign out_byte_en = mem_addr == 32'h1000_0000; + + always @(posedge clk) begin + if (mem_valid && (mem_addr >> 2) < MEM_SIZE) begin + if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; + if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; + if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; + if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; + end + end +endmodule |