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| author | Clifford Wolf <clifford@clifford.at> | 2016-12-15 12:48:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-12-15 13:11:26 +0100 |
| commit | ca5702c75f50c2aba17d1495039fdcbab13f8987 (patch) | |
| tree | 315c37c1cdd98c8bfd2e24f6060c9649dbd968c9 /scripts | |
| parent | 72d6f6f72d43b1b7d203219ad509cf8bd7487de3 (diff) | |
| download | picorv32-ca5702c75f50c2aba17d1495039fdcbab13f8987.tar.gz picorv32-ca5702c75f50c2aba17d1495039fdcbab13f8987.zip | |
Fixed "make test_synth"
Diffstat (limited to 'scripts')
| -rw-r--r-- | scripts/yosys/synth_sim.ys | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys index b64e7e1..ded89d9 100644 --- a/scripts/yosys/synth_sim.ys +++ b/scripts/yosys/synth_sim.ys @@ -1,7 +1,8 @@ # yosys synthesis script for post-synthesis simulation (make test_synth) read_verilog picorv32.v -chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi +chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \ + -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi hierarchy -top picorv32_axi synth write_verilog synth.v |